A new DFT implementation incorporating distributed arithmetic with the DFT is reported. This method proves to be faster and to require less area than the direct implementation of the FFT. >

A fast implementation of the distributed arithmetic discrete Fourier transform

A new architecture has been developed to reduce the instruction-time execution of a microprocessor compatible with the Intel 80C51. This higher performance is achieved by executing all instructions in a minimum number of clock cycles. Dual edge-triggered flip-flops, selective clocking of components, and a hardware-oriented structure are incorporated to produce a processor which has better throughput and lower power dissipation than the Intel 80C51. The new architecture focuses on combining increased performance with low power dissipation. >

Design and synthesis of an Intel 80C51-compatible microprocessor optimized for reduced instruction-time execution

A new design methodology is used to evaluate the difference in performance when implementing the same design using two different ASIC libraries. Multiple dimensions of the design space are considered yielding a better evaluation of the design in hand. An arithmetic logic unit (ALU) is designed using both a standard cell library and a data path library. A cost function is evaluated for both cases and the results are confirmed by fabricating both designs. >

D. Bouldin

Papers

A fast implementation of the distributed arithmetic discrete Fourier transform

Design and synthesis of an Intel 80C51-compatible microprocessor optimized for reduced instruction-time execution

Pre-design consideration and evaluation for ASICs