Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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FPGA Architecture: Survey and Challenges

Multiple word/bit line redundancy techniques at the chip level are shown to be powerful enough to obtain good yields for chips with much higher rates of faults/chip than without redundancy. This is possible because, in many instances, chips which are rejected as being bad still have a high percentage of usable bits on them. The redundancy techniques described consist of putting spare decoders and spare word and bit lines on a chip in order to be able to replace defective lines of the chip with good lines while still maintaining the same address. Based on a first-pass design of a 16K chip, a significant improvement in the number of usable bits per wafer appears possible. The leverage for improvement is shown to be strongly dependent upon the type of cell, the layout, and the technology used.

Multiple word/bit line redundancy for semiconductor memories

This paper discusses the emission of both substrate and channel hot electrons from the silicon into the gate insulator of n-channel IGFET's. In each case the discussion begins with a physical model to elucidate the many parametric dependencies. The effect of changing important material and geometrical parameters as well as temperature and terminal voltages is documented with emission data. Under proper conditions the majority of emitted hot electrons are collected at the gate electrode, so that electron heating can be studied by directly observing gate current. In addition, gate current is a sensitive probe of trapping effects in the gate insulator, and it is shown how these measurements can be used to deduce long-term stability in IGFET structures.

Hot-electron emission in N-channel IGFET's

A new FET device configuration for electrically programmable memories (EPROM), flash/electrically erasable and programmable read-only memories (EEPROM), and non-volatile Random Access Memory (NVRAM) which adds vertical components to a previously planar floating gate cell structure; efficiency of electron injection from the channel to floating gate is enhanced by many orders of magnitude because electrons accelerated in the channel penetraite in the direction of movement, straight into the floating gate. The floating gate resides over a series of arbitrary horizontal and vertical channel region components, the key topological feature being that the vertical channel resides near the drain, allowing electrons to penetrate straight into the floating gate. In contrast, the prior art relies on the indirect process of electron scattering by phonon and the 90 degree upward redirection of motion to the floating gate used by conventional Channel Hot Electron EPROM and EEPROM cells. With the feature of the vertical injection step, high injection efficiency can be achieved at much lower operating voltages, and program time is decreased, which has been a limiting factor in EEPROM applications. Operation at lower voltages improves reliability and overall process complexity. The feature of high injection efficiency at low drain voltage also makes multi-level storage easier and more controllable since the storage of electrons can be controlled by a single control gate voltage. This high efficiency, low voltage, step channel enables a single polysilicon EPROM transistor. Also, a double polysilicon EEPROM transistor with the vertical injection step near drain can achieve erase capability of polysilicon to polysilicon, something that could only be practically built with a triple polysilicon EEPROM cell, in prior art. This combination of a low voltage program and poly to poly erase in a double polysilicon split gate cell with the vertical injection step achieves the non-volatile RAM feature of write 0 (program) or 1 (erase) for a selected word line (control gate) at once. Fabrication methods for the vertical injection step channel near drain are also be described.

Low voltage EEPROM/NVRAM transistors and making method

Two specific examples of the application to computer memories of order-disorder transitions in amorphous semiconductors are discussed. The particular physical changes utilized and accompanying the order-disorder transition are a resistance change and an optical change. The resistance change is applied to an electrically alterable Read-Mostly memory (RMM) and the optical change to a laser-alterable mass memory. The characteristics and mechanisms involved in each application are discussed briefly. The unique role of each memory in its respective area of applicability is described. For the RMM, the impact of manufacturing cost on array structure is discussed, and a new improved array of amorphous devices integrated with silicon is disclosed. For the amorphous mass memory, the effect of the interaction between high bit density laser addressing and practical engineering on the physical form of the first mass memory are discussed.

The application of amorphous materials to computer memories

A novel MOS charge storage transistor developed for an electrically-programmable ROM will be described. The memory element is a fully-decoded 2048-bit silicon gate MOS chip that provides access times of 500 ns (dynamic mode) or 800 ns (static mode).

http://ieeexplore.ieee.org/iel6/8285/25917/01154978.pdf

D. Frohman-Bentchkowsky

Papers

A fully-decoded 2048-bit electrically-programmable MOS ROM