Polymorphic mesh uses physical mesh connection to form twelve useful connection patterns for each of the processing elements making up an image procssor of cellular automata under software control. Each processing element includes a limited mesh of interconnections to related processing elements. This provides for programmable choice of network configuration. The limited mesh of network interconnection is controlled by information stored in a register within the affected processing element. The interconnection pattern controlled by this information is invoked by programming, or by the combination of programming and process data, so as to configure the network of processing elements dynamically in the desired mesh. Representative configurations are: string; mesh; tree; cube; pyramid.

Polymorphic mesh network image processing system

A spatially-oriented information processor which simulates the motions of rigid objects

Abstract In this paper Cylindrical Dielectric Resonator Antenna (CDRA) has been designed for X-band frequency range applications with slot feeding. Bandwidth of designed cylindrical dielectric resonator antenna has been enhanced by making the slot to be resonating and inserting very thin low permittivity dielectric layer between the slot and CDRA. Resonating slot excites the closely spaced HEM11δ and HEM21δ mode inside the antenna as well as provides the resonance at the upper side of desired X-band. Low profile low permittivity layer provides the excellent matching of these modes and shift the HEM21δ mode to higher frequency side at 11.25 GHz with better impedance matching. By combining all of three resonances, nearly 85 % increment in impedance Bandwidth has been obtained with reference to non resonating slot excited CDRA. Fractional impedance bandwidth for proposed design is 48 % and average Gain of 6 dB with more than 92 % radiation efficiency has been shown by the antenna throughout the desired band with broadside pattern.

Bandwidth Enhancement of Cylindrical Dielectric Resonator Antenna Using Thin Dielectric Layer Fed by Resonating Slot

SUMMARY

This paper describes a new approach to histoquantitation which makes fuller use of the visual expertise of the microscopist, provides a permanent visual two-dimensional coded record, and allows mathematical exploitation of the collected data.



The microscopic image of the specimen is traced directly onto computer data cards. A simple sketch records accurate quantitative data for areas and boundaries of as many components of the image as required, in a matrix of 840 points. Spatial relationships are maintained. The matrix is transferred by an Optical Mark Data Card Reader into a computer for extraction of a maximum of information.

Histoquantitation using computer data cards.

In this paper, we describe the performance measurement of a new DSP processor based on the dataflow execution model. Our proposed DSP processor is in contrast to most recent DSP processors based on von Neumann paradigm. We call our DSP as LSC-Based DSP because it is a specialized Loop Structured Computer (LSC) which is a parallel dataflow computer developed in our laboratory. In our measurement, we choose a vector operation as a benchmark algorithm because a vector operation is involved in most DSP algorithms and inherently equivalent to a program in a dataflow computer. LSC-Based DSP is designed in hardware description language and implemented on a field programmable gate array (FPGA). We measure the execution time of a vector operation on LSC-Based DSP with varying some design parameters. The measurement result shows the ability for parallel execution of LSC-Based DSP with several dataflow processing elements. In practice, the execution time of LSC-Based DSP with seven processing elements is approximately five times shorter than that with one processing element.

Execution time measurement of a vector operation on LSC-Based DSP

Techniques currently under investigation for use in the processing of 2-dimensional patterns are reported. Particular reference is made to the design of a parallel-processing computer which is being developed for this task, and some preliminary applications in the segmentation and feature-detection phases of the recognition of handwritten alphanumeric characters are outlined.

Parallel-processing computer for pattern recognition

Pattern-recognition applications of binary-valued orthogonal transforms require only a small number of the possible transform-domain coefficients to be calculated. This letter describes hardware capable of calculating a subset of Walsh-transform coefficients from 2-dimensional patterns.

D.J. Woollons

Papers

Parallel-processing computer for pattern recognition

Implementation of 2-dimensional Walsh transforms for pattern recognition