VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

Machine-learning-based test methods for analog/RF devices have been the subject of intense investigation over the last decade. However, despite the significant cost benefits that these methods promise, they have seen a limited success in replacing the traditional specification testing, mainly due to the incurred test error which, albeit small, cannot meet industrial standards. To address this problem, we introduce a neural system that is trained not only to predict the pass/fail labels of devices based on a set of low-cost measurements, as aimed by the previous machine-learning-based test methods, but also to assess the confidence in this prediction. Devices for which this confidence is insufficient are then retested through the more expensive specification testing in order to reach an accurate test decision. Thus, this two-tier test approach sustains the high accuracy of specification testing while leveraging the low cost of machine-learning-based testing. In addition, by varying the desired level of confidence, it enables the exploration of the tradeoff between test cost and test accuracy and facilitates the development of cost-effective test plans. We discuss the structure and the training algorithm of an ontogenic neural network which is embodied in the neural system in the first tier, as well as the extraction of appropriate measurements such that only a small fraction of devices are funneled to the second tier. The proposed test-error-moderation method is demonstrated on a switched-capacitor filter and an ultrahigh-frequency receiver front end.

/pdf/error-moderation-in-low-cost-machine-learning-based-analog-277e8p6xi0.pdf

Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing

This paper presents a wide-bandwidth, high dynamic range, BiCMOS RF rms detector based on the dynamic translinear principle. A current-domain circuit carries out the main computation, and a circuit compensates for errors due to finite transistor gain. Wide-bandwidth input and output circuits allow connecting voltage-mode signals to the internal current-mode circuitry. Measurements on a prototype chip demonstrate that the circuit is suitable for embedded on-chip testing, particularly for "alternative test" of RF circuits.

A translinear RMS detector for embedded test of RF ICs

This article describes a set of on-chip testing techniques and their application to integrated wireless RF transceivers. The objective is to reduce final product cost and accelerate time to market by providing means of testing the entire transceiver system as well as its major building blocks without using off-chip analog or RF instrumentation. On-chip test devices fabricated in a standard CMOS process and experimentally evaluated support the proposed test strategy

On-Chip Testing Techniques for RF Wireless Transceivers

Increasing levels of integration and high speeds of operation have made the problem of testing complex systems-on-packages (SOPs) very difficult. Testing packages with multigigahertz RF and optical components is even more difficult as external tester costs tend to escalate rapidly beyond 3 GHz. The extent of the problem can be gauged by the fact that test cost is approaching almost 40% of the total manufacturing cost of these packages. To alleviate test costs, various solutions relying on built-off test (BOT) and built-in test (BIT) of embedded high-speed components of SOPs have been developed. These migrate some of the external tester functions to the tester load board (BOT) and to the package and the die encapsulated in the package (BIT) in an "intelligent" manner. This paper provides a discussion of the emerging BOT and BIT schemes for embedded high-speed RF/analog/mixed-signal circuits in SOPs. The pros and cons of each scheme are discussed and preliminary available data on case studies are presented.

D. Keezer

Papers

Low-cost test of embedded RF/analog/mixed-signal circuits in SOPs