In this paper, new upper and lower bounds are obtained for the number of gates in parallel prefix circuits with minimum depth when the number of inputs is a power of two. In addition, structural information concerning these circuits is described. Parallel prefix circuits with bounds imposed on the fan-out of the gates are also considered. In both cases, the upper and lower bounds obtained differ by small constant factors.

New bounds for parallel prefix circuits

We present the design of a VLSI processor which can be programmed to compute the discrete Fourier transform of a sequence of n points and which achieves the theoretical AT2 lower bound of ?(n2) for n ? n where n is an infinite set. Furthermore, since the set n is also sufficiently dense, the processor achieves for any n the theoretical AT2 lower bound of ?(n2) for computing the cyclic convolution of two sequences of n points. Uniquely, our design achieves this bound without the use of data shuffling or long wires. Also, the processor uses only approximately ?n multipliers, while many other designs need ?(n) multipliers to achieve the same time bounds. Since multipliers are usually much larger than adders, the processor presented in this paper should be smaller. The design also features layout regularity, minimal control, and nearest neighbor interconnect of arithmetic cells of a few different types. These characteristics make it an ideal candidate for VLSI implementation.

The Arithmetic Cube

In this paper, we present lower and upper bounds on the size of limited width, bounded and unbounded fan-out parallel prefix circuits. The lower bounds on the sizes of such circuits are a function of the depth, width, and number of inputs. The size requirement of an N input bounded fan-out parallel prefix circuit having limited width W and extra depth k (the difference between allowed and minimum possible depth) is shown to be Ω(N log2
W/2
 k
 + N) for k ≤ log2
W. This implies that insisting on minimum depth causes the circuit size to be nonlinear, while as little as log2log2
W of extra depth can possibly reduce the size to linear. Also, we show that there is a clear difference between the two cases of bounded and unbounded fan-out by proving the size of a limited width, unbounded fan-out parallel prefix circuit lies between a lower bound of Ω((2 + 21−k
/3)N) and an upper bound of O((2 + 21−k
)N). Uniform, systolic constructions of limited width parallel prefix circuits are provided here and shown to be asymptotically optimal. By associating the width of the circuit with the number of processors and the fan-out capabilities of the circuit with the interconnection structure of a multiprocessor, time- and processor-efficient algorithms may be developed.

Limited width parallel prefix circuits

An architecture for a VLSI FFT processor

This paper examines the error performance and presents simulation results of the Arithmetic Cube. The Arithmetic Cube is a special purpose architecture for computing high speed convolution and the DFT. An error analysis is performed for convolution and the DFT, as computed on the Cube. An upper bound on the number of bits lost is derived. The Cube looses at most an extra two bits (four bits), while computing convolution (DFT), more than the number of bits lost if computed by the direct, limited precision convolution (DFT). A VHDL description of the Cube was written and simulations were run. Simulation results substantiate the derived upper bounds. A comparison of the Winograd Fourier-transform-algorithm (WFTA), computed by the Cube, and a rounded FFT, shows that the Cube is at least as accurate as the rounded FFT. Contrary to previous results, it is argued that the WFTA performs better, with respect to accuracy, than the Prime Factor Algorithm (PFA), if both are computed on the Cube. >

The Arithmetic Cube: error analysis and simulation

The construction of Fast Fourier Transform (FFT) processors is discussed. Pipeline and parallel-pipeline organizations are developed and are shown to meet the constraints imposed by VLSI. Various circuit technologies for the construction of these processors are compared, and the description of a set of NMOS chips are given. A technique for reducing the latency of the adders internal to the chips is also presented. Finally, a broad set of possible FFT organizations is discussed.

VLSI implementation of digital fourier transforms

In the late 1970''s a modular, high-throughput architecture for large scale Fourier Transform processors was developed in [1,2]. This architecture uses only a few basic modules in a highly pipelined arrangement and some serial memory for temporary storage of operands. This streamlined architecture seemed predestined for implementation with "Charge Transfer Devices", which have proven themselves in many high-speed signal processing applications and for serial memory [3]. Thus we proposed to investigate the use of charge-coupled devices (CCDs) in the implementation of pipelined FFT processors. For various reasons which are explained below, the use of CCD''s was dropped at an early stage and the decision was made to design these same modules with standard silicon-gate NMOS technology.

D. Lioupis

Papers

VLSI implementation of digital fourier transforms

VLSI Implementation of Digital Fourier Transforms, Final Report