The design of a CMOS current-mode, high-speed, fuzzy logic microprocessor on a chip is described. The design has the advantage of simple circuit structure and high processing speed. The chip consists of approximately 2500 transistors and can process in parallel 40 rules of two antecedents and one conclusion each, at a speed of 1,000,000 FLIPS (fuzzy logic inferences per second) with a 30-MHz clock designed for a 2- mu m CMOS process. As an example of approximate reasoning for application the authors have designed a real-time fuzzy hardware expert system based on the fuzzy microprocessor for the decision-making purposes of a simple intelligent manipulator, searching for a target. The simulation results show that this fuzzy hardware system does accurate, reliable, and real-time planning for the attitude of movement of the manipulator. >

A CMOS current-mode high speed fuzzy logic microprocessor for a real-time expert system

The function of an analog-to-quaternary (A/Q) converter is to convert an analog input voltage into a quaternary output word. In this correspondence, a simple simultaneous analog-to-quaternary converter which makes use of new current-mode quaternary threshold logic circuits is described.

A simultaneous analog-to-quaternary converter

A new explanation of quaternary Q gate expression in Post algebra is given in this paper by using transmission function theory proposed in [1] and the quaternary ECL Q gate circuit is designed. The SPICE2 simulation to this circuit has confirmed that it has desired logical function and is totally compatible with various quaternary ECL circuits proposed before.

Design of quaternary ECL Q gate

Power optimization is an essential issue in designing digital circuits that are battery-powered and portable. The market demands and technical constraints have already necessitated the importance of efforts in advancing energy-efficient circuits. Power minimization is possible by capacitance decrease, activity factor, device and voltage scaling improvement using various encoding schemes, speed performance restrictions, and so on. With the advancement of technology and tremendous efforts by researchers worldwide, its limiting values are approaching, although it remains a concern. Many academicians are attempting to apply various optimization and energy-saving techniques to VLSI circuit design in the current scenario. The problem is resolved transformed and optimized to extract the desired power-aware design with advantages from the conventional methods. After studying different energy-saving strategies, adiabatic logic seems to be the perfect choice to reduce energy usage in VLSI circuits. The primary idea behind adiabatic logic circuits is to reduce power dissipation by slowing the change from logic “0” to “1” and vice versa. Adiabatic logic circuits can be implemented using a variety of techniques. The researchers carried out a detailed analysis of combinational and sequential circuits in the literature. This chapter discusses combinational and sequential circuit design using various adiabatic approaches. Analysis of various parameters like transistor count, delay, power dissipation, and power delay product is carried out. It has been analyzed that adiabatic circuits perform better than traditional methods. 

Study of Adiabatic Logic-Based Combinational and Sequential Circuits for Low-Power Applications

Parallel counters are multiple input circuits that count the number of their inputs that are in a given state. In this paper, the implementation of parallel counters with four-valued threshold logic is described and these implementation are compared to their binary full adder network counter equivalents. Since each signal variable in four-valued logic may assume four logic states, twice the information carrying capacity as in binary logic, an over fifty percent savings in the total number of signal variables required to implement the parallel counter results. With the circuits we describe here, fifty percent fewer transistors and resistors are necessary for the implementation of four-valued logic parallel counters.

D. Mow

Papers

Parallel counter design using four-valued threshold logic