Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems The promise of the technology is to create a brain-like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed

A Survey of Neuromorphic Computing and Neural Networks in Hardware.

A switch, switched architecture and process for transferring data through an FCAL switch is disclosed. The switch uses multiple switch control circuits each coupled to one FCAL network and all connected to a crossbar switch. The switch control circuits are coupled together by a protocol bus for coordination purposes. Local conversations can occur on each FCAL loop and crossing conversations through the switch can occur concurrently. The OPN primitive is used to establish the connection before any data is transferred thereby eliminating the need for buffer memory in the switch control circuits. The destination address of each OPN is used to address a lookup table in each switch control circuit to determine if the destination node is local. If not, the destination is looked up and a connection request made on the protocol bus. If the remote port is not busy, it sends a reply which causes both ports to establish a data path through the backplane crossbar switch.

Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost

This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

/pdf/vlsi-implementations-of-threshold-logic-a-comprehensive-vqkiwr19v2.pdf

VLSI implementations of threshold logic-a comprehensive survey

We present a new fast reconstruction algorithm for parallel beam tomography. The new algorithm is an accelerated version of the standard filtered backprojection (FBP) reconstruction, and uses a hierarchical decomposition of the backprojection operation to reduce the computational cost from O(N/sup 3/) to O(N/sup 2/log/sub 2/N). We discuss the choice of the various parameters that affect the behavior of the algorithm, and present numerical studies that demonstrate the cost versus distortion tradeoff. Comparisons with Fourier reconstruction algorithms and a multilevel inversion algorithm by Brandt et al., both of which also have O(N/sup 2/log/sub 2/N) cost, suggest that the proposed hierarchical scheme has a superior cost versus distortion performance. It offers RMS reconstruction errors comparable to the FBP with considerable speedup. For an example with a 512/spl times/512-pixel image and 1024 views, the speedup achieved with a particular implementation is over 40 fold, with reconstructions visually indistinguishable from the FBP.

O(N/sup 2/log/sub 2/N) filtered backprojection reconstruction algorithm for tomography

Recent dramatic improvements in integrated circuit fabrication technology have led to Field-Programmable Gate Arrays (FPGAs) capable of implementing entire digital systems, as opposed to the smaller logic circuits that have traditionally been targeted to FPGAs. Unlike the smaller circuits, these large systems often contain memory. Architectural support for the efficient implementation of memory in next-generation FPGAs is therefore crucial.
This dissertation examines the architecture of FPGAs with memory, as well as algorithms that map circuits into these devices. Three aspects are considered: the analysis of circuits that contain memory, as well as the automated random generation of such circuits, the architecture and algorithms for stand-alone configurable memory devices, and architectures and algorithms for the embedding of memory arrays in an FPGA.
We first present statistics gathered from 171 circuits with memory. These statistics include the number of memories in each circuit and the width and depth of these memories. We identify common interconnect patterns between memory and logic. These statistics are then used to develop a circuit generator that stochastically generates realistic circuits with memory that can be used as benchmark circuits in architectural studies.
Next, we consider the architecture of a stand-alone configurable memory that is flexible enough to implement memory configurations with different numbers of memories, memory widths and depths. Instrumental in this work is the algorithms that map memory configurations to the device. These algorithms are used in an experimental framework to investigate the effect of various architectural parameters on the flexibility, chip area, and access time of the configurable memory.
Finally, the architecture of an FPGA containing both embedded memory arrays and logic elements is considered, along with new automatic placement and routing algorithms that map circuits to the FPGA. We show that only 4 switches per memory block pin are required in the interconnection between the memory arrays and logic elements, and even lower in FPGAs with four or fewer memory arrays. In addition, we show that by providing direct connections between memory arrays, the FPGA density can be improved slightly, and the average memory access time can be improved by as much as 25%.

Architectures and algorithms for field-programmable gate arrays with embedded memory

Current-mode CMOS circuits are receiving increasing attention. Current-mode CMOS multiple-valued logic circuits are interesting and may have applications in digital signal processing and computing. In this paper we review several of the current-mode CMOS multiple-valued logic (MVL) circuits that we have studied over the past decade. These circuits include a simple current threshold comparator, current-mode MVL encoders and decoders, current-mode quaternary threshold logic full adders (QFAs), current-mode MVL latches, current-mode latched QFA circuits, and current-mode analog-to-quaternary converter circuits. Each of these circuits is presented and its performance described. >

Current-mode CMOS multiple-valued logic circuits

The first VLSI digital signal processor that performs both high-precision image backprojection and spatial histogram calculations at raster-scan rates as high as 30 MHz is described. Realized in 1 mu m CMOS technology, this 13.3 mm*13.3 mm chip is designed to handle images as large as 1024*1024 12 b pixels. Loadable coefficients and a unified architecture allow this IC to be used with a variety of computed-tomography scanners for image reconstructions, including fan- and parallel-beam reconstruction. This chip also computes the forward Radon transform, which is a spatial histogram, permitting it to be used for iterative reconstruction algorithms. The bit lengths in the fixed-point architecture assure 12 b reconstruction accuracy. >

An image processing IC for backprojection and spatial histogramming in a pipelined array

The accuracy and speed characteristics of implementations of several line integration models required for Radon (1917) transform (used for computed tomography image reconstruction) and backprojection computations are described and compared. The fixed-point number system used is evaluated by error comparisons to identical floating-point calculations. An expandable multiprocessor architecture for high-speed computation that has been realized as a prototype using commercially available digital signal processor (DSP) chips as the basic processing elements is described. The simulated performances of two popular DSP chips for this application are discussed and compared. Performance characteristics of the complete prototype hardware system are presented. The computational speed of a four-chip system is measured to be more than 190 times better than that of a Sun 3/160 with a math coprocessor. The architecture and prototype organization are not dependent on the DSP chip chosen, and substitution of the most up-to-date DSP chips can yield even better speed performance. >

High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architecture

Current-mode CMOS multiple-valued logic circuits that are compatible with many previously proposed CMOS artificial neural network circuits are discussed. Current-mode circuitry for generating multiple-valued weighted sums of currents, performing arithmetic operations, and for comparing multiple-valued (quantized) signal currents to action threshold current are presented. Memory circuits capable of storing the multiple-valued currents are presented. An experimental evaluation of several of the circuits is presented. >

http://ieeexplore.ieee.org/iel5/143/3356/00112634.pdf

CMOS current-mode circuits for neural networks

A new voltage-mode CMOS multiple-valued logic (MVL) memory circuit has been realized in a standard 2 μm p-well polysilicon-gate CMOS technology. This circuit requantizes MVL voltages during a setup clock mode and latches the input value during the hold clock mode. Using a 5 V supply and logical voltage increments of 1 -67 V, a quaternary memory circuit with a worst-case total setup and hold time of about 7 ns, and a best single-level transition total setup and hold lime of about 1 ns has been realized.

K.W. Current

Papers

Current-mode CMOS multiple-valued logic circuits

An image processing IC for backprojection and spatial histogramming in a pipelined array

High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architecture

CMOS current-mode circuits for neural networks

Multiple-valued logic memory circuit