DC–DC converters with voltage boost capability are widely used in a large number of power conversion applications, from fraction-of-volt to tens of thousands of volts at power levels from milliwatts to megawatts. The literature has reported on various voltage-boosting techniques, in which fundamental energy storing elements (inductors and capacitors) and/or transformers in conjunction with switch(es) and diode(s) are utilized in the circuit. These techniques include switched capacitor (charge pump), voltage multiplier, switched inductor/voltage lift, magnetic coupling, and multistage/-level, and each has its own merits and demerits depending on application, in terms of cost, complexity, power density, reliability, and efficiency. To meet the growing demand for such applications, new power converter topologies that use the above voltage-boosting techniques, as well as some active and passive components, are continuously being proposed. The permutations and combinations of the various voltage-boosting techniques with additional components in a circuit allow for numerous new topologies and configurations, which are often confusing and difficult to follow. Therefore, to present a clear picture on the general law and framework of the development of next-generation step-up dc–dc converters, this paper aims to comprehensively review and classify various step-up dc–dc converters based on their characteristics and voltage-boosting techniques. In addition, the advantages and disadvantages of these voltage-boosting techniques and associated converters are discussed in detail. Finally, broad applications of dc–dc converters are presented and summarized with comparative study of different voltage-boosting techniques.

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Step-Up DC–DC Converters: A Comprehensive Review of Voltage-Boosting Techniques, Topologies, and Applications

Due to the continuous power supply reduction, charge pumps circuits are widely used in integrated circuits (ICs) devoted to several kind of applications such as smart power, nonvolatile memories, switched capacitor circuits, operational amplifiers, voltage regulators, SRAMs, LCD drivers, piezoelectric actuators, RF antenna switch controllers, etc. The main focus of this tutorial manuscript is to provide a deep understanding of the charge pumps behavior, to present useful models and key parameters and to organically and in details discuss the optimized design strategies. Finally, an overview of the main different topologies is also included.

Charge Pump Circuits: An Overview on Design Strategies and Topologies

An 8-channel closed-loop neural-prosthetic SoC is presented for real-time intracranial EEG (iEEG) acquisition, seizure detection, and electrical stimulation in order to suppress epileptic seizures. The SoC is composed of eight energy-efficient analog front-end amplifiers (AFEAs), a 10-b delta-modulated SAR ADC (DMSAR ADC), a configurable bio-signal processor (BSP), and an adaptive high-voltage-tolerant stimulator. A wireless power-and-data transmission system is also embedded. By leveraging T-connected pseudo-resistors, the high-pass (low-pass) cutoff frequency of the AFEAs can be adjusted from 0.1 to 10 Hz (0.8 to 7 kHz). The noise-efficiency factor (NEF) of the AFEA is 1.77, and the DMSAR ADC achieves an ENOB of 9.57 bits. The BSP extracts the epileptic features from time-domain entropy and frequency spectrum for seizure detection. A constant 30- μA stimulus current is delivered by closed-loop control. The acquired signals are transmitted with on-off keying (OOK) modulation at 4 Mbps over the MedRadio band for monitoring. A multi-LDO topology is adopted to mitigate the interferences across different power domains. The proposed SoC is fabricated in 0.18- μm CMOS and occupies 13.47 mm2. Verified on Long Evans rats, the proposed SoC dissipates 2.8 mW and achieves high detection accuracy (> 92%) within 0.8 s.

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A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control

This paper compares the performances of vibration-powered electrical generators using a piezoelectric ceramic and a piezoelectric single crystal associated to several power conditioning circuits. A new approach of the piezoelectric power conversion based on a nonlinear voltage processing is presented, leading to three novel high performance power conditioning interfaces. Theoretical predictions and experimental results show that the nonlinear processing technique may increase the power harvested by a factor of 8 compared to standard techniques. Moreover, it is shown that, for a given energy harvesting technique, generators using single crystals deliver 20 times more power than generators using piezoelectric ceramics.

Single crystals and nonlinear process for outstanding vibration-powered electrical generators

The Boltzmann machine is a massively parallel computational model capable of solving a broad class of combinatorial optimization problems. In recent years, it has been successfully applied to training deep machine learning models on massive datasets. High performance implementations of the Boltzmann machine using GPUs, MPI-based HPC clusters, and FPGAs have been proposed in the literature. Regrettably, the required all-to-all communication among the processing units limits the performance of these efforts. This paper examines a new class of hardware accelerators for large-scale combinatorial optimization and deep learning based on memristive Boltzmann machines. A massively parallel, memory-centric hardware accelerator is proposed based on recently developed resistive RAM (RRAM) technology. The proposed accelerator exploits the electrical properties of RRAm to realize in situ, fine-grained parallel computation within memory arrays, thereby eliminating the need for exchanging data between the memory cells and the computational units. Two classical optimization problems, graph partitioning and boolean satisfiability, and a deep belief network application are mapped onto the proposed hardware. As compared to a multicore system, the proposed accelerator achieves 57x higher performance and 25x lower energy with virtually no loss in the quality of the solution to the optimization problems. The memristive accelerator is also compared against an RRAM based processing-in-memory (PIM) system, with respective performance and energy improvements of 6.89x and 5.2x.

Memristive Boltzmann machine: A hardware accelerator for combinatorial optimization and deep learning

In this paper, an optimized strategy for designing charge pumps with minimum power consumption is presented. The approach allows designers to define the number of stages that, for a given input, and an output voltage, maximize power efficiency. Capacitor value is then set to provide the current capability required. This approach was analytically developed and validated through simulations and experimental measurements on 0.35-/spl mu/m EEPROM CMOS technology. This approach was then compared with one which minimized the silicon area and it was shown that only a small increase in area is needed to minimize power consumption.

Charge-pump circuits: power-consumption optimization

A variable charge pump contains several individual simple charge pumps, each with a pumping capacitor and a switching mechanism. Additionally, a switching network is coupled to the individual charge pumps so that the different lines in the charge pump can be connected together in a serial mode or parallel mode (or mixed serial and parallel modes) to match the needs of the output load. The switching network is easily changed to provide the necessary driving capability as the needs of the output load changes.

Variable stage charge pump

A charge pump that changes its number of stages while maintaining the same total charge pump capacitances is presented. The charge pump dynamically modifies the number of stages through a feedback that rearranges the topology of the set capacitor minimising power consumption. The circuit is then discussed analytically and validated through transistor-level simulations by using 0.18 μm EEPROM technology.

Charge pump with adaptive stages for non-volatile memories

Protecting the devices of a charge pump includes the connection of a high-voltage transistor between the output node of the charge pump and the load being supplied, and in controlling this transistor with a fraction of the output voltage of the charge pump. This control is accomplished by connecting the control node of the high-voltage transistor to a node of connection between two stages of the multi-stage charge pump onto which a fraction of the controlled output voltage of the multi-stage charge pump is produced. The high-voltage output transistor protects the low voltage devices of the multi-stage charge pump, by preventing the controlled output voltage from undergoing excessively abrupt variations, that could damage the transistors of the last stage of the charge pump.

D. Pappalardo

Papers

Charge Pump Circuits: An Overview on Design Strategies and Topologies

Charge-pump circuits: power-consumption optimization

Variable stage charge pump

Charge pump with adaptive stages for non-volatile memories

Multi-stage charge pump voltage generator with protection of the devices of the charge pump