In many computational tasks, especially in signal processing, it is the throughput that is important, rather than the latency, or delay. If a special-purpose VLSI chip is designed for a particular signal processing task, such as FIR filtering, for example, the maximum clock rate, and hence throughput, is determined by the depth of the combinational logic between registers and the time required for the distribution and operation of the clock. If the combinational logic is sufficiently deep (in bit-parallel circuits, for example), the throughput can be increased by inserting intermediate stages of clocked latches. This is at the expense of increased area and delay to operate and clock the intermediate registers. Roughly speaking, the strategy amounts to using more of the chip area to store information useful for pipelining. This paper investigates the optimal tradeoff between the degree of intermediate latching and cost, using the measure AP, where A is the chip area and P is the period (the reciprocal of throughput). We derive expressions for the time and area before and after intermediate latching, using the Mead-Conway model, both for the cases of on-chip and off-chip clock drivers. The results show that significant reductions in AP product (reciprocal of throughput per unit area) can be achieved by intermediate latching in many typical signal processing applications, for a wide range of circuit parameters. The array multiplier is used as an example.

Optimal choice of intermediate latching to maximize throughput in VLSI circuits

The number of representation and the range of floating-point numbers is treated for floating-point signal processing. The addition and multiplication operations which are most important for digital signal processing are explained in detail including the necessary normalization operations. Quantization errors in terms of the probability densities of the relative errors are analyzed in detail for roundoff-quantization, two's-complement-truncation, and magnitude-truncation. The roundoff-noise is determined for a single quantizer and for complex signal processing flowgraphs. The problem of limit cycles is discussed briefly. >

Floating-point signal processing-arithmetic, roundoff-noise, and limit cycles

This paper investigates the optimal tradeoff between the degree of intermediate latching and cost in special-purpose VLSI chips, using the measure AP, where A is the chip area and P is the period (the reciprocal of throughput). The results show that significant reductions in AP-product (reciprocal of throughput per unit area) can be achieved by-intermediate latching in many typical signal processing applications, for a wide range of circuit parameters.

For programmable high-speed digital signal processing devices the proper architecture has to be carefully selected according to the algorithms to be implemented. The appropriate number of arithmetic units depends on the degree of parallelism of the signal processing algorithm. The question of parallelism of algorithms is discussed. For the efficient exploitation of a given signal processor hardware, an appropriate processor schedule is necessary. In two examples different approaches for multiprocessor architectures are discussed. >

http://ieeexplore.ieee.org/iel5/143/3356/00112398.pdf

Parallel architectures for programmable high-speed signal processing devices

Many signal processing algorithms are highly regular, data-independent, and access the data in fixed patterns. For these reasons the current technological advances in very large scale integrated circuits hold especially great promise for signal processing, and in fact we now see the development of many highly integrated processors of a more or less specialized nature. At one end of the spectrum, we see programmable signal processing chips that are really microprocessors, with program, memory and logic separated as in a general purpose machine. At the other extreme, we see highly-specialized, custom chips that perform fixed tasks; typically the data moves through the chip along fixed, regular paths, the arithmetic logic is distributed in space, and the “program” is really “hard-wired” into the topology. This talk is devoted to a study of this latter, custom variety of architecture.

Hierarchical, Parallel and Systolic Array Processing

Recent advances in technology of VLSI circuits enable economical hardware implementation of highly sophisticated signal processing algorithms. This provides the capability of realising a signal processor with uniform hardware for wide real-time applications. The adaption of the VLSI circuits to special application is possible by appropriate microprograms. The processor speed is determined by the arithmetic unit, particularly if floating point arithmetic is necessary. The processing speed can be increased by decreasing the operation time of the arithmetic unit and by the use of several adders, several multipliers, multiport memory and pipeline technique.

D. Wesseling

Papers

Integrated floating point signal processor