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Proceedings ArticleDOI

Integrated floating point signal processor

K. Bottcher, +3 more
- Vol. 7, pp 1088-1091
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TLDR
Recent advances in technology of VLSI circuits enable economical hardware implementation of highly sophisticated signal processing algorithms that provides the capability of realising a signal processor with uniform hardware for wide real-time applications.
Abstract
Recent advances in technology of VLSI circuits enable economical hardware implementation of highly sophisticated signal processing algorithms. This provides the capability of realising a signal processor with uniform hardware for wide real-time applications. The adaption of the VLSI circuits to special application is possible by appropriate microprograms. The processor speed is determined by the arithmetic unit, particularly if floating point arithmetic is necessary. The processing speed can be increased by decreasing the operation time of the arithmetic unit and by the use of several adders, several multipliers, multiport memory and pipeline technique.

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Journal ArticleDOI

Optimal choice of intermediate latching to maximize throughput in VLSI circuits

TL;DR: The results show that significant reductions in AP product (reciprocal of throughput per unit area) can be achieved by intermediate latching in many typical signal processing applications, for a wide range of circuit parameters.
Proceedings ArticleDOI

Floating-point signal processing-arithmetic, roundoff-noise, and limit cycles

TL;DR: The number of representation and the range of floating-point numbers is treated and the roundoff-noise is determined for a single quantizer and for complex signal processing flowgraphs.
Proceedings ArticleDOI

Optimal choice of intermediate latching to maximize throughput in VLSI circuits

TL;DR: The results show that significant reductions in AP-product can be achieved by-intermediate latching in many typical signal processing applications, for a wide range of circuit parameters.
Proceedings ArticleDOI

Parallel architectures for programmable high-speed signal processing devices

TL;DR: In two examples different approaches for multiprocessor architectures are discussed, the question of parallelism of algorithms is discussed and an appropriate processor schedule is necessary.
Book ChapterDOI

Hierarchical, Parallel and Systolic Array Processing

TL;DR: This talk is devoted to a study of this latter, custom variety of architecture of highly-specialized, custom chips that perform fixed tasks.