A low-cost and high-gain on-chip terahertz (THz) dielectric resonator antenna (DRA) is proposed in this work. The DRA consists of a low-loss dielectric resonator (DR) made of high-resistivity silicon material and an on-chip feeding patch realized in a 0.18-μm CMOS technology for exciting the desired electromagnetic (EM) mode. The DR can be easily fabricated to the required dimension by wafer dicing of a 2-in silicon wafer. With a 500-μm thick DR, a higher order mode of TE δ, 1 , 7 can be excited, which greatly enhances the antenna gain. Such higher order mode operation also provides a reliable design. If a fundamental mode is selected, the DR thickness is around 100 μm at THz frequencies, which not only requires an additional wafer thinning process, but the wafer is also easily broken during the fabrication process. The feeding patch is used to excite the TE δ, 1 , 7 mode. Moreover, its ground plane also prevents the EM field from leaking into the lossy CMOS silicon substrate, which improves the antenna efficiency. The simulated antenna gain can be 7.9 dBi while providing radiation efficiency of 74% at 341 GHz with 7.3% bandwidth. To characterize the DRA performance, an identical CMOS imager is designed to be integrated with the proposed DRA and an on-chip patch antenna. By comparing the measured responsivity of these two imagers, the gain improvement of the DRA over the on-chip patch antenna can be obtained. Three samples are measured to evaluate the robustness of the proposed antenna over process variation. The measured results show that the maximum gain improvement of 6.7 dB can be acquired at 327 GHz. The proposed DRA with the integrated CMOS imager is also employed to successfully demonstrate a THz transmissive imaging system at 327 GHz. To the best of authors’ knowledge, this is first higher order mode DRA working at THz frequencies.

340-GHz Low-Cost and High-Gain On-Chip Higher Order Mode Dielectric Resonator Antenna for THz Applications

A low-power and high-performance 340-GHz heterodyne receiver front end (RFE) optimized for terahertz (THz) biomedical imaging applications is proposed in this paper. The THz RFE consists of an on-chip patch antenna, a single-balanced mixer, and a triple-push harmonic oscillator. The oscillator adopts a proposed harmonic oscillator architecture which can provide differential output by extracting output signals from the same current loop without any additional balun required. The mixer biased in the subthreshold region is designed not only to have high conversion gain and low noise figure by choosing the output intermediate frequency well above the flicker-noise corner frequency, but the required local oscillator (LO) power can also be as low as –11 dBm. Such a low demand on the LO power makes the proposed mixer very suitable for THz applications in which the achievable LO power is very limited. The impact of unavoidable slots for passing design rule checks on the performance of an on-chip patch antenna is also presented. The proposed THz RFE is implemented in a 40-nm digital complementary metal–oxide–semiconductor technology. The measured voltage conversion gain is –1.7 dB at 335.8 GHz, while the mixer and the oscillator only consume 0.3 and 52.8 mW, respectively, from a 1.1 V supply. The proposed THz RFE is employed to set up a THz transmissive imaging system which can provide spatial resolution of 1.4 mm.

A 340-GHz Heterodyne Receiver Front End in 40-nm CMOS for THz Biomedical Imaging Applications

This oscillator uses a single-emitter 0.3- m InP heterojunction bipolar transistor (HBT) device with maximum frequency of oscillation (fmax) greater than 500 GHz. Due to high conductor and substrate losses at submillimeterwave frequencies, a primary challenge is to efficiently use the intrinsic device gain. This was done by using a suitable transmission-line media and circuit topology. The passive components of the oscillator are realized in a twometal process with benzocyclobutene (BCB) used as the primary transmission line dielectric. The circuit was designed using microstrip transmission lines. The oscillator is implemented in a common-base topology due to its inherent instability, and the design includes an on-chip resonator, outputmatching circuitry, and an injection-locking port, the port being used to demonstrate the injection-locking prin ciple. A free-running frequency of 311.6 GHz has been measured by down-converting the signal. Ad di tionally, injection locking has been successfully demonstrated with up to 17.8 dB of injection-locking gain. The injection-locking reference signal is generated using a 2 20 GHz frequency synthesizer, followed by a doubler, active tripler, a W-band amplifier, and then a passive tripler. Therefore, the source frequency is multiplied 18 times to obtain a signal above 300 GHz that can be used to injection lock the oscillator. Measurement shows that injection locking has improved the phase noise of the oscillator and can be also used for synchronizing a series of oscillators. A signal conductor is implemented near the BCP -InP interface and the topside of the BCB layer is fully metallized as a signal ground. Because the fields are primarily constrained in the lower permittivity BCB region, this type of transmission line is referred to as an inverted microstrip. In addition, both common-emitter and commonbase circuits were investigated to determine optimum topology for oscillator design. The common -base topology required smaller amount of feedback than the common-emitter design, therefore preserving device gain, and was chosen for the oscillator design. The submillimeter-wave region offers several advantages for sensors and communication systems, such as high resolution and all-weather imaging due to the short-wavelength, and improved communication speeds by access to greater frequency bandwidth. This oscillator circuit is a prototype of the first HBT oscillator operating above 300 GHz. Additional development is necessary to increase the output power of the circuit for radar and imaging applications.

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A 311-GHz Fundamental Oscillator Using InP HBT Technology

A low-cost terahertz transmitter is proposed by using system-on-package (SoP) heterogeneous system integration. A signal source in 40-nm CMOS is integrated with an antenna array on a Benzocyclobutene carrier through a broadband low-loss terahertz interconnect. The signal source adopting triple-push oscillator topology is able to produce a differential output without any additional balun circuit. Hence, the power consumption and the chip area can be reduced. The antenna array containing 50 patch antennas is differentially excited to give simulated directivity, efficiency, and antenna gain as high as 22.6 dB, 88%, and 22 dBi, respectively, at 335 GHz. The terahertz interconnect employs a resonator coupling technique to provide low-loss and broadband performance while occupying a small area. Measured results show that the proposed terahertz transmitter can work at 338.4 GHz with equivalent isotropically radiated power (EIRP) of 8.0 dBm while consuming only 37.5 mW from a 1-V supply. The measured half-power beam-width can be as narrow as 15.5 $^{\circ}$ . The EIRP can be further raised to 9.5 dBm as the supply $V_{ DD}$ is increased to 1.3 V. The CMOS chip only occupies an area as small as 0.028 ${\hbox {mm}}^{2}$ . All of the design efforts enable the proposed terahertz transmitter to feature in small form factor, low power dissipation, low cost, and high performance. To the best of the authors' knowledge, this is the most compact, lowest power, lowest cost, and high-performance SoP-based terahertz transmitter reported thus far.

A 37.5-mW 8-dBm-EIRP 15.5 $^{\circ}$ -HPBW 338-GHz Terahertz Transmitter Using SoP Heterogeneous System Integration

This article presents a high fundamental frequency subterahertz (sub-THz) CMOS oscillator with a single core. The proposed structure with a capacitive load reduction circuit increases the fundamental oscillation frequency by decreasing the parasitic capacitances of the buffer transistor and inductor and minimizing the loss caused by the gate resistance of the buffer stage. To achieve high output power, the proposed oscillator combines the differential output signals through a differential-to-single (DTS) transformer. A push–push oscillator based on the high fundamental frequency oscillator is also introduced to increase the operating frequency further. The proposed oscillators are implemented in a 65-nm CMOS process. Measurements of the fundamental oscillator reveal an output power of 0.285 mW at 251 GHz, while consuming 21 mA from a 1.3-V supply voltage. The measured operating frequency of the push–push oscillator is 432 GHz.

A High Fundamental Frequency Sub-THz CMOS Oscillator With a Capacitive Load Reduction Circuit

A low-power triple-push oscillator with differential output is proposed in this letter. By extracting signals from the same current loop, the oscillator can naturally provide differential output without any additional active circuit or passive balun required. Therefore, the output power can be increased and the chip area and power consumption can be reduced. Realized in 40 nm CMOS technology, the proposed oscillator can oscillate at 340.6 GHz while providing equivalent isotropically radiated power (EIRP) as -21.8 dBm. The power consumption is only 34.1 mW from a 0.9 V supply. The oscillator core only occupies area of 0.028 mm
 2
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https://ir.nctu.edu.tw:443/bitstream/11536/124113/1/000345903500015.pdf

Da Chiang Chang

Papers

A 340 GHz triple-push oscillator with differential output in 40 nm CMOS