The present invention relates to a disk drive recording apparatus and more particularly to a method for optimizing performance of a read channel in a disk drive recording apparatus by using an error rate. The method for optimizing performance of a read channel in a disk driving recording apparatus having a programmable low-pass filter and a control device for controlling apparatus operation includes the steps of initially assigning a filtering characteristic to the programmable low-pass filter as a predetermined initial bandwidth value via the control device; detecting and evaluating data written on a predetermined track of a disk to calculate a first data detection error rate by the control device; comparing a reference error rate with the first data detection error rate; setting the filtering characteristic of the low-pass filter to a bandwidth indicating a lowest error rate by varying the bandwidth of the programmable low-pass filter when the first data detection error rate is greater than a reference error rate; thereafter, detecting data written on the predetermined track of the disk to calculate a second data detection error rate by the control device; comparing the reference error rate with the second data detection error rate; outputting an error state signal indicating that the disk drive recording apparatus is in an error state when the second data detection error rate is greater than the reference error rate; and setting a currently set bandwidth as a final set value and completing an optimization process when any one of the first and second data detection error rates is below the reference error rate.

Method of optimizing read channel of disk drive recording apparatus by using error rate

A playback clock signal generating circuit has first and second phase-locked loops PLLs. The first PLL has a voltage-controlled oscillator VCO controllable by an output signal from a low-pass filter for outputting a signal, a variable frequency divider for varying a frequency-dividing number depending on head position information and frequency-dividing the signal from the VCO with the varied frequency-dividing number, a reference oscillator for outputting a reference signal having a frequency equal to a predetermined frequency step, a phase comparator for detecting the phase or frequency difference between an output signal from the variable frequency divider and the reference signal, and outputting the detected phase or frequency difference to the low-pass filter. The second PLL has a VCO controllable by a low-pass filter for outputting a signal, a mixer for frequency-converting the signal from the VCO with the signal from the VCO of the first PLL to output a playback clock signal, and a phase comparator for detecting the phase difference between a reproduced data signal and the playback clock signal and outputting the detected phase difference to the low-pass filter.

Playback clock signal generating circuit which uses a first and second phase lock loop

A phase comparator for comparing the relative phase of a first input signal and a second input signal. The phase comparator detects a slipping condition, the slipping condition present if the first input signal leads the second input signal in phase and the first input signal is delayed for at least one cycle such that a first rising edge of the first input signal lags a first rising edge of the second input signal by greater than 180°. The phase detector resets at least one output of the phase comparator upon the detection of the slipping condition. Also described are circuits to implement the phase comparator and a transconductance compensation circuit for a filter, and methods of comparing phase and transconductance compensation.

Transconductance compensation circuit having a phase detector circuit with cycle slipping recovery operation and method

A method and apparatus for calibrating an analog equalizer in a sampled amplitude read channel is disclosed wherein the filter's frequency response is measured and calibrated directly. This is accomplished by injecting a known periodic signal into the analog filter and measuring a spectrum value at a predetermined frequency. The filter parameters are adjusted accordingly until the spectrum reaches a predetermined target value. In the preferred embodiment, the analog filter comprises at least one second order low pass filter (referred to as a biquad filter), and the filter's spectrum is adjusted relative to the well known parameters f o and Q. Specifically, the parameters f o and Q are optimized relative to a power measurement at predetermined harmonics of the input signal. In this manner, the present invention enables auto-calibration of the analog equalizer without reading any data from the disc. Furthermore, the calibration process can be executed during the storage system's normal operation without significantly degrading its overall performance.

Method and apparatus for calibrating an analog filter in a sampled amplitude read channel

A servo gate method and apparatus to allow switching between a servo mode and a data mode in the read channel of a disk drive. The present invention uses a servo gate signal to select components and parameters in the read channel of a disk drive. The servo gate signal, when enabled, preloads appropriate registers with new values and preloads the programmable filter with new values. The servo gate signal is not limited to preloading the above values, but may be used to control many characteristics of a disk drive read channel. For example, the servo gate signal may be used to control a pulse detector amplitude voltage threshold, to select between a window comparator and a hysteresis comparator, to control a pulse detector qualification mode for either a window comparator or a hysteresis comparator, to set a hysteresis threshold time constant, to adjust the cut-off frequency and high-frequency boost of a programmable filter, to switch a raw data output, to set an AGC amplifier gain setting, to provide fast recovery from changes in offset or DC operating point changes and to set an AGC amplifier target voltage level. The servo gate signal is designed to override read gate and write gate signals.

Method and apparatus for switching between data and servo modes

An arrangement for tuning a data filter in a mass storage system. The filter cutoff frequency (low pass) may be set as a percentage above or below the incoming data rate to achieve the desired "eye opening" in read data. The frequency of a reference oscillator in a phase-locked-loop (PLL) and the cutoff frequency of the filter is controlled by a common control signal from the PLL. The PLL, locked to a scaled multiple of the data rate, determines the cutoff frequency of the filter.

Dale H. Nelson

Papers

Data filter tuning for constant density recording applications