Dramatic improvements in SAT solver technology over the last decade and the growing need for more efficient and scalable verification solutions have fueled research in verification methods based on SAT solvers. This paper presents a survey of the latest developments in SAT-based formal verification, including incomplete methods such as bounded model checking and complete methods for model checking. We focus on how the surveyed techniques formulate the verification problem as a SAT problem and how they exploit crucial aspects of a SAT solver, such as application-specific heuristics and conflict-driven learning. Finally, we summarize the noteworthy achievements in this area so far and note the major challenges in making this technology more pervasive in industrial design verification flows.

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A survey of recent advances in SAT-based formal verification

IEEE transactions on very large scale integration (VLSI) systems

Reconfigurable architectures can bring unique capabilities to computational tasks. They offer the performance and energy efficiency of hardware with the flexibility of software. In some domains, they are the only way to achieve the required, real-time performance without fabricating custom integrated circuits. Their functionality can be upgraded and repaired during their operational lifecycle and specialized to the particular instance of a task. We survey the field of reconfigurable computing, providing a guide to the body-of-knowledge accumulated in architecture, compute models, tools, run-time reconfiguration, and applications.

Reconfigurable Computing Architectures

Propositional Satisfiability (SAT) and Constraint Programming (CP) have developed as two relatively independent threads of research cross-fertilizing occasionally. These two approaches to problem solving have a lot in common as evidenced by similar ideas underlying the branch and prune algorithms that are most successful at solving both kinds of problems. They also exhibit differences in the way they are used to state and solve problems since SAT's approach is, in general, a black-box approach, while CP aims at being tunable and programmable. This survey overviews the two areas in a comparative way, emphasizing the similarities and differences between the two and the points where we feel that one technology can benefit from ideas or experience acquired from the other.

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Propositional Satisfiability and Constraint Programming: A comparative survey

Today's computers must perform with increasing reliability, which in turn depends on the problem of determining whether a circuit has been manufactured properly or behaves correctly. However, the greater circuit density of VLSI circuits and systems has made testing more difficult and costly. This book notes that one solution is to develop faster and more efficient algorithms to generate test patterns or use design techniques to enhance testability - that is, "design for testability." Design for testability techniques offer one approach toward alleviating this situation by adding enough extra circuitry to a circuit or chip to reduce the complexity of testing. Because the cost of hardware is decreasing as the cost of testing rises, there is now a growing interest in these techniques for VLSI circuits.The first half of the book focuses on the problem of testing: test generation, fault simulation, and complexity of testing. The second half takes up the problem of design for testability: design techniques to minimize test application and/or test generation cost, scan design for sequential logic circuits, compact testing, built-in testing, and various design techniques for testable systems.Hideo Fujiwara is an associate professor in the Department of Electronics and Communication, Meiji University. Logic Testing and Design for Testability is included in the Computer Systems Series, edited by Herb Schwetman.

Logic testing and design for testability

In this paper we present a new approach to implement satisfiability (SAT) on reconfigurable hardware. Given a combinational circuit C, we automatically design a SAT circuit whose architecture implements a branch-and-bound SAT algorithm specialized for C. A major novel feature is that both the next variable to assign and its value are dynamically determined by a backward model traversal done in hardware. Our approach relies on fine-grain massive parallelism.

Satisfiability on reconfigurable hardware

This paper develops a novel approach for formally verifying both safety and liveness properties of designs using sequential ATPG tools. The properties are automatically mapped into a monitor circuit with a target fault so that finding a test for the fault corresponds to formally establishing the property. The mapping of the properties to the monitor circuit is described in detail and the process is shown to be sound and complete. Experimental results show that the ATPG-based approach performs better than existing verification techniques, especially for large designs.

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Verifying Properties Using Sequential ATPG

Satisfiability (SAT) is a computationally expensive algorithm central to many CAD and test applications. In this paper, we present the architecture of a new SAT solver using reconfigurable logic. Our main contributions include new forms of massive fine-grain parallelism and structured design techniques based on iterative logic arrays that reduce compilation times from hours to a few minutes. Our architecture is easily scalable. Our results show several orders of magnitude speed-up compared with a state-of-the-art software implementation, and with a prior SAT solver using reconfigurable hardware.

A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware

Here we demonstrate the feasibility of micro-electro-mechanical system (MEMS) functional devices where a single device functions as a logic gate. This novel approach reduces the number of MEMS devices needed to implement a mechanical processor by a factor of 10. MEMS processors are suitable for operation in harsh environment in engines and in the presence of ionizing radiations inside nuclear reactors or in space applications. MEMS devices have overall lower speed and are less reliable than the complementary metal-oxide-semiconductor (CMOS) devices. By reducing the number of devices needed for a given operation, our approach improves yield, reproducibility, speed and simplifies implementation of MEMS circuits such as adders and multiplexers. Specifically, we discuss XOR and AND gates fabricated on Si 3 N 4 and polysilicon as bridge materials using W electrodes. The XOR gates with ∼1.5 V turn-on voltage at 50 MHz with >10 9 cycles of reliable operations and low operational power consumption (leakage current −9  A at V  ∼ 0.5 V, and power

Single-device “XOR” and “AND” gates for high speed, very low power LSI mechanical processors

Industry is beginning to use Satisfiability (SAT) solvers extensively for formally verifying the correctness of digital designs. In this paper we compare the performance of SAT solvers with sequential Automatic Test Pattern Generation (ATPG) techniques for property verification. Our experimental results on the ISCAS benchmarks as well as a model of the 8085 microprocessor show that, contrary to popular belief, ATPG techniques perform much better than SAT based verification techniques, especially for large designs.

Daniel G. Saab

Papers

Satisfiability on reconfigurable hardware

Verifying Properties Using Sequential ATPG

A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware

Single-device “XOR” and “AND” gates for high speed, very low power LSI mechanical processors

Formal verification using bounded model checking: SAT versus sequential ATPG engines