Daniel Wu

TL;DR: This paper describes the design of a fully-adaptive backplane transceiver embedded in a state-of-the-art, low-leakage, 28nm CMOS FPGA, and a novel clocking technique uses wideband LC and ring oscillators for reliable clocking from 0.6-12.5Gb/s operation.

TL;DR: The paper describes the design of a 0.6-13.1Gb/s fully-adaptive backplane transceiver embedded in state-of-the-art low-leakage 28nm CMOS FPGAs, and investigates the major challenges in the designs of high-speed reconfigurable transceivers.

TL;DR: The introduction of high-speed backplane transceivers inside FPGAs has addressed critical issues such as the ease in scalability of performance, high availability, flexible architectures, the use of standards, and rapid time to market.

TL;DR: Integration techniques enable the utilization of the transceiver in FPGAs with both wire-bond and flip-chip packages and resolve significant challenges with receiver input and transmitter output insertion loss, power integrity, ESD, and reliability.

TL;DR: This paper describes the design techniques to achieve wideband flexible-reach operation in a fully-adaptive transceiver embedded in a 20nm CMOS FPGA with modified 11-tap, 1bit speculative DFE topology that meets jitter tolerance specifications for both PCIe Gen3 and PCIe Gen4 at 16Gb/s in both common-clock and spread-spectrum modes.