This paper reviews electrostatic discharge (ESD) investigations on laterally diffused MOS (LDMOS) and drain-extended MOS (DeMOS) devices. The limits of the safe operating area of LDMOS/DeMOS devices and device physics under ESD stress are discussed under various biasing conditions and layout schemes. Specifically, the root cause of early filament formation is highlighted. Differences in filamentary nature among various LDMOS/DeMOS devices are shown. Based on the physical understanding, device optimization guidelines are given. Finally, an outlook on technology scaling is presented.

A Review on the ESD Robustness of Drain-Extended MOS Devices

The root causes of the high voltage (HV) LDMOS (Fig. 2) failed at the low voltage electrostatic-discharge (ESD) zap is found. One is caused by the bulk layout and one is caused by the intrinsic characteristic of the device. From the findings, a new structure is proposed to eliminate the root causes without sacrificing the IV characteristics and dimension of the device.

The influence of the layout on the ESD performance of HV-LDMOS

For high-voltage output driver, the lateral DMOS (LDMOS) is often used for both output function operation and self-protection against electrostatic discharge (ESD) events. In this work, a new structure of LDMOS output device with embedded SCR has been proposed and verified in a 0.25-μm 60-V BCD process. This new structure, with additional p+ and n+ implantation regions added between the drain contact and poly-gate of LDMOS, can keep it stably in the high-current holding region after snapback. By using this structure, the LDMOS can provide high enough self-protected ESD robustness for applications in the high-voltage output drivers.

Self-protected LDMOS output device with embedded SCR to improve ESD robustness in 0.25-μm 60-V BCD process

A new kind of ESD failure mechanism is found in the UHV 700V LDNMOS during the HBM ESD zapping event. The device is damaged by its own charges and board stored charges, not damaged by the HBM stress current. The device junction capacitor and test-board capacitor store the charges from the ESD tester before the avalanche breakdown occurring. After the avalanche breakdown, the two capacitors discharge the stored charges to give the additional currents to stress the device. This phenomenon is called the charged-capacitor model (CCM) [1].

The ESD failure mechanism of ultra-HV 700V LDMOS

This paper investigates the electrostatic discharge (ESD) failure mechanism in the human body model of circular ultrahigh voltage lateral diffused MOS-type devices. Failure occurs due to the current crowding effect at the N+ junction edge of the drain adjacent to the field oxide. Instead of a large single N+ diffusion, a novel drain design with small multidiffusions is proposed to eliminate the current crowding and to enhance its ESD performance.

A Novel Drain Design for ESD Improvement of UHV-LDMOS

In this letter, the dynamic turn-on mechanism of the n-MOSFET under high-current-stress event is investigated by using a real-time current and voltage measurement. Results reveal the existence of ldquoself-consistent effect,rdquo i.e., the turn-on region of the parasitic n-p-n bipolar can change from one region to another region and increases with the stress current (ID). Furthermore, experimental data show that the minimum substrate potential to sustain a stable snapback phenomenon is 0.9 V and increases with ID instead of 0.6-0.8 V and independent of ID as reported in early literatures.

Dynamic Turn-On Mechanism of the n-MOSFET Under High-Current Stress

The influence of the internal circuit layout on the chip CDM performance is reported in this paper. It is found that the well pick-up has great impact on the chip CDM performance. The well pick-up can sink the CDM current into the P-Well and induce the non-uniform current to stress the device. This paper also verifies that the bus-line capacitors are more important than the package capacitor for chip CDM since the well pick-up only can affect the current coming from bus line capacitors, but cannot affect the current coming from the package capacitor. Moreover, putting the circuit and ESD protection device in the deep-NWell to isolate the circuit from the P-substrate and using the long contact-to-contact space for ESD protection device also can get the better CDM performance.

The study of sensitive circuit and layout for CDM improvement

A novel ESD device structure with non-LDD at drain region has been demonstrated to enhance the ESD immunity of IO circuits with mixed high/low operation voltage. The protection capability of this novel ESD device structure has been proved from 1 mum to 65 nm technologies with and without fully salicide at the source/drain region. This structure is found to be also very effective to protect the high voltage tolerant (HVT) IO circuits and the drain extended NMOSFET (DEMOS) transistors. The ESD failure thresholds can be improved from HBM < 0.5 KV and MM < 50 V to HBM 4 KV and MM 200 V, respectively. In addition, this novel ESD device structure is cost effective because two process modules including RPO and ESD implant can be removed.

Dao-Hong Yang

Papers

The influence of the layout on the ESD performance of HV-LDMOS

Dynamic Turn-On Mechanism of the n-MOSFET Under High-Current Stress

The study of sensitive circuit and layout for CDM improvement

A novel ESD device structure with fully silicide process for mixed high/low voltage operation