A device independent, frequency driven layout system and method for field programmable gate arrays ("FPGA") which allow for a circuit designer to specify the desired operating frequencies of clock signals in a given design to the automatic layout system to generate, if possible, a physical FPGA layout which will allow the targeted FPGA device to operate at the specified frequencies. Actual net, path and skew requirements are automatically generated and fed to the place and route tools. The system and method of the present invention evaluates the frequency constraints, determines what delay ranges are acceptable for each electrical connection and targets those ranges throughout the layout.

Frequency driven layout system and method for field programmable gate arrays

A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners using a static timing analysis module, and estimating performance of the circuit at a predetermined confidence level based on results of the statistical analysis during an automated design flow of the circuit without using libraries at the predetermined confidence level.

Systems, methods, and apparatus to perform statistical static timing analysis

The invention is a method of designing an integrated circuit in which the steps of designing the circuit are optimized by a formal hierarchy. This method, called Timing Driven Placement, of designing an integrated circuit avoids detailed optimization which consumes enormous computational resources. It organizes physical and logical characteristics of the design so that those characteristics can be optimized with respect to the physical design of the circuit. The characteristics are optimized and the resulting circuit to location assignment is placed and wired with a conventional automated process. The method optimizes the global placement into precincts of logic segments of the circuit design with respect to the segment placement effect on circuit timing and wireability. The method then migrates individual circuits within particular segments to other segments to improve both the individual segment and overall circuit timing and wireability. Finally, the method transfers circuit assignment to logic segment and logic segment assignment to physical location information to a conventional process for final detailed circuit placement and wiring.

Timing driven placement

The present invention provides suggested delay limits for use by layout tools which cause a programmable integrated circuit device to implement a logic design. The suggested delay limits can be used by such tools as an initial placement algorithm, a placement improvement algorithm, and a routing algorithm for evaluating and guiding potential layouts. The suggested delay limits take into account characteristics of the programmable device being used by estimating lower bound delays for each connection in a logic design, and take into account any previously achieved delays or achievable delays for each connection in calculating the suggested limits. Results of routing benchmark designs using the novel suggested limits show improved timing performance for all benchmark cases tested.

Timing driven method for laying out a user's circuit onto a programmable integrated circuit device

A digital circuit simulation method and apparatus provide for critical path timing analysis of digital circuitry using a hybrid path tracing method. The hybrid path tracing performs path tracing when, for example, simulation values change at designated inputs. The path tracing can employ the simulation values for eliminating blocked paths. During tracing, the method and apparatus determine the shortest and longest paths from each input or beginning point to each end point. The end points are typically storage elements such as latches, flip-flops or systems outputs at a high functional level. The critical path tracing analysis finds the shortest and longest paths from the beginning point to the end point and records and saves the violation history, if any, associated with those paths. A timing template allows the user to develop the necessary input stimuli, in a logical ordered format to test the timing behavior of the digital circuit to be designed. Special procedures are also available for enabling the iteration of stimuli to check the timing of a transparent latch-based design. The system thus provides as an output either a summary or detailed history of violations at selected levels within the circuit to be analyzed. User input enables the system to isolate upon particular portions of the circuitry for determining correct operation.

Method and apparatus for verifying timing during simulation of digital circuits

The time verification scheme of the present invention operates without input stimulus to calculate delays along circuit paths including logic elements or cells from initial input to final output, or over sub-circuit paths, of a proposed logic design. The delay calculations include cell-dependent, and layout-dependent, and environmental-dependent factors to account for response delays on rising and falling signal; capacitance loading, temperature-dependency and voltage-dependency of a proposed logic design to provide output histograms and reports of information about overall performance, and timing violations of the proposed logic design with respect to operating parameters that can be selectively adjusted for manufacturing variations.

Darrell R. Parham

Papers

Static timing analysis of semiconductor digital circuits