On the convective thermal performance of a CPU cooler working with liquid gallium and CuO/water nanofluid: A comparative study

Semiconductor manufacturers aim to fabricate defect-free wafers in order to improve product quality, increase yields, and reduce costs. Typically, wafer defects form spatial patterns that provide useful information, helping to identify problems and faults during the fabrication process. Machine learning (ML) methods have been used to classify these defects in order to locate the root causes of failure. This paper proposes a novel deep-structured ML approach as an extension of our previous randomized general regression network (RGRN) model, to identify and classify both single-defect and mixed-defect patterns. The principal motivation for this paper is that a shallow-structured RGRN performs well on single-pattern defects, achieving an accuracy of 99.8%, but performs poorly when a wafer has mixed-defect patterns. The proposed approach improves RGRN performance, particularly on mixed-pattern defects, by incorporating a novel information gain (IG)-based splitter as well as deep-structured ML. A spatial filter is applied to remove random noise and reduce model bias during training. During the first detection stage, the splitter generates unique rules that are built using the IG theory and splits the defects data into single-defect and mixed-defect patterns. Single-defect patterns are then classified by RGRN, whereas mixed-defect patterns are fed into the deep-structured ML model for further classification. This combination improves the ability of the proposed approach to classify diverse defect patterns and achieve a better overall performance. Our experimental results demonstrate that the proposed approach achieves an overall detection accuracy of 86.17% on a dataset that contains real data representing both single-defect and mixed-defect patterns, as commonly found in real manufacturing scenarios, outperforming existing ML-based models.

Deep-Structured Machine Learning Model for the Recognition of Mixed-Defect Patterns in Semiconductor Fabrication Processes

Accurate prediction of cycle time (CT) plays an important role in the promises of a good delivery-time for semiconductor manufacturers. However, the CTs of wafer lots are difficult to forecast since they are influent by a lot factors (e.g., workload for every machine). The identification of key factors (called CT-related) can not only improve the prediction performance but also facilitate the control of CT, which is of particular significance. This paper focuses on gathering subtle variables into the candidate variables set along with the further analysis which is required in the correlation analysis between various candidate factors and CTs of wafer lots. The candidates set is first constructed to collect all factors that may affect wafer lots’ CT. Then, a regression-based model is proposed to select CT-related variables, which consists of three parts: 1) discretization; 2) adaptive logistic regression-based correlation analysis; and 3) CT-related factor selection. Subsequently, a parallel computation model is implemented to forecast the CTs of wafer lots. In the numerical experiments, 108 CT-related factors stood out from 774 candidates and replaced six global factors (used as reference) to predict CTs of wafer lots. The results indicated that the proposed approach had higher accuracy than linear regression and back propagation network in CT forecasting in large scale data analysis.

A Data Driven Cycle Time Prediction With Feature Selection in a Semiconductor Wafer Fabrication System

A novel bi-piezoelectric jet dispenser with a zoom mechanism is proposed to distribute adhesives rapidly. The work frequency of the new jet dispenser can reach 500 Hz. The volume of the minimum dot is about 25 nL, and the volume error among dots is not more than ±10%. The dot size can be controlled by adjusting the driving voltage of the piezoelectric stack, filling pressure, and the opening time of the valve. Subsystem physical models of the jet valve are presented on the basis of the bi-piezoelectric principle and the zoom mechanism, which involves an electromechanical model, dynamic model, and fluid–solid coupling model. Based on these physical models, a coupled mechanical–electrical fluid simulation model is established, which can be simulated. The simulation results of the multiphysics-coupled model are in accordance with the experiment. The coupling model will develop a reliable simulating platform for high-speed fluid jet. The effectiveness of the bi-piezoelectric method and models is confirmed, and it will provide a new technology for microelectronics packaging.

A Novel High-Speed Jet Dispenser Driven by Double Piezoelectric Stacks

Through silicon via (TSV)-based 3-D integrated circuit has introduced the solution to limitlessly growing demand on high system bandwidth, low power consumption, and small form factor of electronic devices. As the system design aims for higher performance, the physical dimensions of the channels are continuously decreasing. With TSV diameter of less than 10 $\mu \text{m}$ and pitch of several tens of micrometers, the I/O count has increased up to the order of tens of thousands for wide bandwidth data transmission. However, without highly precise fabrication process, such small structures are susceptible to a variety of defects. For the first time, in this paper, we propose a noninvasive defect analysis method for high-speed TSV channel. With designed and fabricated test vehicles, the proposed method is demonstrated with ${S}$ -parameter and time-domain reflectometry measurement results. In addition, we present equivalent circuit models of TSV daisy-chain structures, including the circuit components for open defect and short defect. With characterized dominant factors in each frequency range, $S_{11}$ is analyzed to distinguish and locate the defects by the amount of capacitance, resistance, and inductance that the signal experiences. ${S}$ -parameter measurement sufficiently allows high-frequency defect analysis of TSV channel without destroying the test sample. We experimentally verified the accuracy of the suggested model by comparing the ${S}$ -parameter results from circuit simulations and measurements. Finally, the model is modified to discuss the effects of open defect and short defect on the electrical characteristics of TSV channel.

Through Silicon Via (TSV) Defect Modeling, Measurement, and Analysis

An automatic system based on thermoelectric cooler (TEC), a microfan, and microcontroller is first applied to thermal management of high-power light-emitting diodes (LEDs). Its hardware is composed of microcontroller as a control core, K-type thermocouples as acquisition devices, and TEC and a microfan with heatsink as cooling vehicles. The experiment confirms that the LEDs substrate temperature can be controlled effectively, and indicates that the LED chips are operating reliably. Specifically, in high-temperature environments of 43 °C, the system can automatically drop to the low set temperature (30 °C) due to thermoelectric effect driven by TEC. Heat transfer analysis shows that maximum LED power cooled by the system is 106.7 W, and the total power consumption of the automatic cooling system is only 8.85 W. The automatic cooling system has a high cooling efficiency.

New Applications of an Automated System for High-Power LEDs

With the fast development of IC (integrated circuit) packaging industry, IC test is becoming more and more important, especially the probe test of the wafer packaging. Based on experimental data and theoretical analysis, an electromechanical model is first proposed to describe the characteristics of the testing process of wafer probe to understand the behavior of micro-probe testing process, and to simulate the whole physical process. The model consists of a dynamic mechanical model, a dc electro-mechanical coupling model and an ac impedance model, which is used to analyze the overall physical properties of the probe test process and has a good agreement with the experimental data. Based on the electromechanical model, a simulation platform is established first, which will provide a simulation tool for the design of the microprobe and setting of multiparameters.

An Electromechanical Model and Simulation for Test Process of the Wafer Probe

In order to investigate the performance of microprobe in integrated circuit (IC) testing, a novel testing system with four-wire cable tester and contact force sensor is deployed using high-density microprobes whose resistance and contact force are automatically measured and saved using LabVIEW. The testing resistance is statistically analyzed for DE1-030EB40-010 type probes with adjusted testing parameters. The results show that the displacement effect is significant for resistance testing. In addition, the testing resistance is not a stable and small value until the displacement exceeds 300 μm. Furthermore, the velocity of microprobe varying from 25 to 40 mm/s leads to a minimum deviation. The life cycle testing experiments indicate that some microprobe life cycles are , whereas other life cycles are only 70000 times. It is also found that the contact force is decreased with the increase of life cycles, whereas the decreased contact force results in poor contact between microprobe and IC, which in turn affects the life cycle of the microprobe.

Dynamic and Electrical Characteristics of Microprobe Testing in Microelectronics Packaging

A testing circuit of probe is designed to understand the real-time characteristics of the probe during testing process. The constant resistance voltage and probe voltage are measured simultaneously by DSOX2022A oscilloscope, and the real-time resistance of probe is calculated. The result shows that the probe resistance varies from the initial infinity to approximately $1~\Omega $ at 0.2 ms when the probe is in contact with the copper substrate. The resistance of the probe is gradually reduced to relatively stable value with the increasing of compressed displacement. The probe resistance increases badly in initial 30 times testing when the angle between probe and copper changes from 0° to 2°, and reduces to a stable value after 20-30 times testing.

Real-Time Voltage and Resistance Features in Microprobe Testing Process

In order to develop integrated circuit (IC) testing, a new system was suggested using a microprobe array, a four-wire tester, machine vision, and motion control technology. The microprobe array can be automatically aligned with the IC die by an image-processing program in the system. It was found that the operating efficiency of the algorithm was improved by six times by extracting the rectangular edge contour. Several image-processing methods were combined and optimized to calculate the deflection angle, and the linear fitting method was improved. Inaccurate fitting was eliminated by the modified fitting method, and the alignment error was significantly reduced. Although IC electrodes were precisely aligned with the microprobe tips, the compressive displacement of the microprobe also has a greater influence on the electrical testing. The testing resistance was not a stable value until the compressive displacement exceeded 100 $\mu \text{m}$ . Finally, the effectiveness of the microprobe automatic testing approach was confirmed. The open circuits of the ICs can be detected, and the resistance of the circuits, which are not open circuits, can be automatically measured and evaluated.

Dasong Ge

Papers

New Applications of an Automated System for High-Power LEDs

An Electromechanical Model and Simulation for Test Process of the Wafer Probe

Dynamic and Electrical Characteristics of Microprobe Testing in Microelectronics Packaging

Real-Time Voltage and Resistance Features in Microprobe Testing Process

A New Automatic Testing System Based on Image Processing and Microprobes for IC-Testing