The matching properties of MOS capacitors are modeled and compared with measured data. A weighted-capacitor array design approach is described. Voltage and temperature dependence of MOS capacitors are analyzed, modeled, and compared with measured data. It is shown that to a first-order heavily doped polysilicon accumulates and depletes similar to crystalline silicon.

Matching properties, and voltage and temperature dependence of MOS capacitors

This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal charge redistribution DAC employs unit capacitance of 0.5 fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40 nm CMOS process achieves 46.8 dB SNDR and 58.2 dB SFDR with 1.1 MS/sec at 0.5 V power supply. The FoM is 6.3-fJ/conversion step and the chip die area is only 160 μm × 70 μm.

A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS

Linearity errors of weighted capacitor digital-to-analog converters (DAC's) can be corrected using a simple digital algorithm. The additional circuitry required is approximately 350 digital gates plus 10 bytes of memory space.

Self-calibration technique for A/D converters

The present invention comprises a circuit for measuring the capacitive differences of small capacitors. The circuit comprises a reference capacitor and a sensor capacitor. Connected to one of the plates of each capacitor is a switch which connects the capacitors to one of two reference voltages. The other plate of the capacitors are connected to an input terminal of a voltage comparator. The comparator compares the input voltage with a third reference voltage. Differences in voltages detected by the comparator are applied to a feedback loop for generating an offset voltage at the input terminal. The offset voltage applied at the input terminal is proportional to the capacitive difference between the reference capacitor and the sensor capacitor. The feedback loop comprises a successive approximation register for digitizing the offset voltages and a digital to analog converter for converting the digitized voltages into analog voltages which are applied at the input terminal. Digitized offset voltages can be measured at the output of the successive approximation register.

Digital technique for precise measurement of variable capacitance

The difference between two capacitors is measured digitally using a charge redistribution technique incorporating a comparator, MOS switches, a successive approximation register, and a digital-to-analog converter. The technique is insensitive to comparator offset and parasitic capacitance, and the effect of MOS switch charge injection is measured and canceled. Extensive measurements have been made from test chips fabricated in 3- mu m CMOS technology. Detection of percent differences of >

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A digital readout technique for capacitive sensor applications

The recent development of integrated circuit capacitor arrays and the growth of their applications have resulted in a need to perform precision testing as an aid to future design improvements. For reasons discussed in this paper, laboratory instruments such as capacitance bridges are not well-suited to this need. In order to test capacitor arrays accurately, a novel technique has been developed. It is based on a special algorithm in which the capacitor array is used as a precision voltage divider. A capacitor array tester consisting of both hardware and software has been built which executes this algorithm. This system has been used to perform measurements upon a large number (thousands) of NMOS and CMOS capacitor arrays. The standard deviation of this tester's measurement error is approximately 0.0009 percent of full scale (0.0088 LSB referenced to 10 bits). In contrast with manual testing with a capacitance bridge (requiring 10 min per array), the tester requires less than 5 s to fully test an array, mark the circuit and move to the next die position.

David A. Sealer

Papers

Precision Capacitor Ratio Measurement Technique for Integrated Circuit Capacitor Arrays