http://bnrg.cs.berkeley.edu/~randy/Courses/CS294.S13/1.3.pdf

Data center evolution

A method for securing remote access to private networks includes a receiver intercepting from a data link layer a packet in a first plurality of packets destined for a first system on a private network. A filter intercepts from the data link layer a packet in a second plurality of packets transmitted from a second system on the private network, destined for an system on a second network. A transmitter in communication with the receiver and the filter performing a network address translation on at least one intercepted packet and transmitting the at least one intercepted packet to a destination.

A method and systems for securing remote access to private networks

Distributed in-memory key-value stores, such as memcached, are central to the scalability of modern internet services. Current deployments use commodity servers with high-end processors. However, given the cost-sensitivity of internet services and the recent proliferation of volume low-power System-on-Chip (SoC) designs, we see an opportunity for alternative architectures. We undertake a detailed characterization of memcached to reveal performance and power inefficiencies. Our study considers both high-performance and low-power CPUs and NICs across a variety of carefully-designed benchmarks that exercise the range of memcached behavior. We discover that, regardless of CPU microarchitecture, memcached execution is remarkably inefficient, saturating neither network links nor available memory bandwidth. Instead, we find performance is typically limited by the per-packet processing overheads in the NIC and OS kernel---long code paths limit CPU performance due to poor branch predictability and instruction fetch bottlenecks.Our insights suggest that neither high-performance nor low-power cores provide a satisfactory power-performance trade-off, and point to a need for tighter integration of the network interface. Hence, we argue for an alternate architecture---Thin Servers with Smart Pipes (TSSP)---for cost-effective high-performance memcached deployment. TSSP couples an embedded-class low-power core to a memcached accelerator that can process GET requests entirely in hardware, offloading both network handling and data look up. We demonstrate the potential benefits of our TSSP architecture through an FPGA prototyping platform, and show the potential for a 6X-16X power-performance improvement over conventional server baselines.

/pdf/thin-servers-with-smart-pipes-designing-soc-accelerators-for-106pe5ymhl.pdf

Thin servers with smart pipes: designing SoC accelerators for memcached

An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.

Method and apparatus for shared I/O in a load/store fabric

An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of operating system domains through a PCI Express fabric. Each of the first plurality of I/O ports is configured to route PCI Express transactions between said plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint, where the first shared input/output endpoint is configured to request/complete said PCI Express transactions for each of the plurality of operating system domains. The core logic is coupled to the first plurality of I/O ports and the second I/O port. The core logic routes the PCI Express transactions between the first plurality of I/O ports and the second I/O port.

Switching apparatus and method for providing shared i/o within a load-store fabric

To meet the increasing networking needs of server workloads, servers are starting to offload packet processing to peripheral devices to achieve TCP/IP acceleration. Researchers at Intel Labs have experimented with alternative solutions that improve the server's ability to process TCP/IP packets efficiently and at very high rates.

/pdf/tcp-onloading-for-data-center-servers-5btfgg2cr9.pdf

TCP onloading for data center servers

An apparatus and a system may include an adaptation module, a plurality of Direct Transport Interfaces DTIs (108), a DTI accelerator (120), and a Transport Control Protocol/Internet Protocol TCP/IP accelerator (150). The adaptation module (104) may provide a translated sockets call from an application program (132) to one of the DTIs, where an included set of memory structures may couple the translated sockets call to the DTI accelerator, which may in turn couple the set of memory structures to the TCP/IP accelerator. An article may include data causing a machine to perform a method including: receiving an application program sockets call at the adaptation module, deriving a translated sockets call from the application program sockets call, receiving the translated sockets call at a DTI, coupling the translated sockets call to a DTI accelerator using a set of memory structures in the DTI, and coupling the set of memory structures to a TCP/IP accelerator.

Embedded transport acceleration architecture

A system having an I/O interconnect topology utilizes internal packetized communications. The system includes a host system element, a plurality of switching elements, and a root complex to bridge communications between the host system and the switching elements. The ports of at least some of the switching elements have a cross-link device associated therewith, which is a logical device defined by configuration space of the switching element. Each cross-link device defines a cross-link communication path between two switching elements of the hierarchy allowing communications between peripherals to bypass the host.

System and method for communicating over intra-hierarchy and inter-hierarchy links

A multiple-domain processing system includes a multi-dimensional switching fabric to provide intra-domain and inter-domain communication within the system.

Multiple-domain processing system using hierarchically orthogonal switching fabric

In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.

David B. Minturn

Papers

TCP onloading for data center servers

Embedded transport acceleration architecture

System and method for communicating over intra-hierarchy and inter-hierarchy links

Multiple-domain processing system using hierarchically orthogonal switching fabric

Header replication in accelerated TCP (Transport Control Protocol) stack processing