There is disclosed in a communications system having an origination storage device and a destination storage device, a data transfer pipeline apparatus for transferring data in a sequence of N stages, where N is a positive integer grater than 1, from the origination to the destination device. The data transfer apparatus comprises dedicated memory means having a predetermined number of buffers dedicated for carrying data associated with the transfer of data from the origination storage device to the destination device; and master control means for registering and controlling processes associated with the data transfer apparatus for participation in the N stage data transfer sequence. The processes include at least a first stage process for initiating the data transfer and a last Nth stage process for completing data transfer. The first stage process is operative to allocate a buffer from the predetermined number of buffers available within the dedicated memory means for collection, processing, and sending of the data from the origination device to a next stage process. The Nth stage process is operative to receive a buffer allocated to the first stage process from the (N−1)th stage process in the data transfer sequence and to free the buffer upon processing completion and storage in the destination device to permit reallocation of the buffer. The master control means further includes monitor means for monitoring the number of buffers from the pool of buffers allocated or assigned to particular processes in the pipeline, in order to prevent allocation of further buffers to a particular process when the number of buffers currently allocated exceeds a predetermined threshold.

Pipelined high speed data transfer mechanism

Performing data management operations on replicated data in a computer network. Log entries are generated for data management operations of an application executing on a source system. Consistency point entries are used to indicate a time of a known good, or recoverable, state of the application. A destination system is configured to process a copy of the log and consistency point entries to replicate data in a replication volume, the replicated data being a copy of the application data on the source system. When the replicated data represents a known good state of the application, as determined by the consistency point entries, the destination system(s) may perform a storage operation (e.g., snapshot, backup) to copy the replicated data and to logically associate the copied data with a time information (e.g., time stamp) indicative of the source system time when the application was in the known good state.

Systems and methods for performing data replication

A modular computer storage system and method is provided for managing and directing data archiving functions, which is scalable and comprehends various storage media as well as diverse operating systems on a plurality of client devices. A client component is associated with one or more client devices for generating archival request. A file processor directs one or more storage devices, through one or more media components, which control the actual physical level backup on various storage devices. Each media component creates a library indexing system for locating stored data. A management component coordinates the archival functions between the various client components and the file processor, including setting scheduling policies, aging policies, index pruning policies, drive cleaning policies, configuration information, and keeping track of running and waiting jobs.

Modular backup and retrieval system used in conjunction with a storage area network

A system and method are provided for performing storage operations relating to a first secondary copy of electronic data. A storage policy or storage preferences may dictate that a replication copy should be used in storage operations performed to a particular client, sub-client, data, media or other item. Based on the storage policy, when a new client, sub-client, data, media or other item is received, a media agent determines whether there is a replication copy of the item. In the absence of a replication copy, one may be created. The replication copy may be provided by a third party application, or created by the client or a storage management system component. Information regarding the replication copy and its corresponding first secondary copy may be stored in a database. To optimize use of system resources, storage operations relating to the first secondary copy may be performed using the replication copy instead of the first secondary copy.

Systems and methods for performing replication copy storage operations

A system and method are disclosed for providing efficient data storage. A plurality of data segments is received in a data stream. The system determines whether a data segment has been stored previously in a low latency memory. In the event that the data segment is determined to have been stored previously, an identifier for the previously stored data segment is returned.

Efficient data storage system

A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and the floating point unit also share a common reorder buffer, register file, branch prediction unit and load/store unit which all reside on the same main data processing bus. Instruction and data caches are coupled to a main memory via an internal address data bus which handles communications therebetween. An instruction decoder is coupled to the instruction cache and is capable of decoding multiple instructions per microprocessor cycle. Instructions are dispatched from the decoder in speculative order, issued out-of-order and completed out-of-order. Instructions are retired from the reorder buffer to the register file in-order. The functional units of the microprocessor desirably accommodate operands exhibiting multiple data widths. High performance and efficient use of the microprocessor die size are achieved by the sharing architecture of the disclosed superscalar microprocessor.

High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations

A data cache configured to perform store accesses in a single clock cycle is provided. The data cache speculatively stores data within a predicted way of the cache after capturing the data currently being stored in that predicted way. During a subsequent clock cycle, the cache hit information for the store access validates the way prediction. If the way prediction is correct, then the store is complete. If the way prediction is incorrect, then the captured data is restored to the predicted way. If the store access hits in an unpredicted way, the store data is transferred into the correct storage location within the data cache concurrently with the restoration of data in the predicted storage location. Each store for which the way prediction is correct utilizes a single clock cycle of data cache bandwidth. Additionally, the way prediction structure implemented within the data cache bypasses the tag comparisons of the data cache to select data bytes for the output. Therefore, the access time of the associative data cache may be substantially similar to a direct-mapped cache access time. The present data cache is therefore suitable for high frequency superscalar microprocessors.

Data cache which speculatively updates a predicted data cache storage location with store data and subsequently corrects mispredicted updates

A load/store unit searches a store queue included therein for each byte accessed by the load independently from the other bytes, and determines the most recent store (in program order) to update that byte. Accordingly, even if one or more bytes accessed by the load are modified by one store while one or more other bytes accessed by the load are modified by another store, the forwarding mechanism may assemble the bytes accessed by the load. More particularly, load data may be forwarded accurately from an arbitrary number of stores. In other words, forwarding may occur up to N stores (where N is the number of bytes accessed by the load). In one particular embodiment, the load/store unit generates a bit vector from a predetermined set of least significant bits of the addresses of loads and stores. The bit vector includes a bit for each byte in a range defined by the number of least significant bits. The bit indicates whether or not the byte is updated (for store bit vectors) or accessed (for load bit vectors). The load/store unit may then examine the bit vectors (and compare the remaining bits of the store and load addresses, exclusive of the least significant bits used to generate the bit vectors) in order to locate the most recent update of each byte.

System for store to load forwarding of individual bytes from separate store buffer entries to form a single load word

A superscalar microprocessor employing a data cache configured to perform store accesses in a single clock cycle is provided. The superscalar microprocessor speculatively stores data within a predicted way of the data cache after capturing the data currently being stored in that predicted way. During a subsequent clock cycle, the cache hit information for the store access validates the way prediction. If the way prediction is correct, then the store is complete, utilizing a single clock cycle of data cache bandwidth. Additionally, the way prediction structure implemented within the data cache bypasses the tag comparisons of the data cache to select data bytes for the output. Therefore, the access time of the associative data cache may be substantially similar to a direct-mapped cache access time. The superscalar microprocessor may therefore be capable of high frequency operation.

Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle

A processor is configured to detect a branch instruction have a forward branch target address within a predetermined range of the branch fetch address of the branch instruction. If the branch instruction is predicted taken, instead of canceling subsequent instructions and fetching the branch target address, the processor allows sequential fetching to continue and selectively cancels the sequential instructions which are not part of the predicted instruction sequence (i.e. the instructions between the predicted taken branch instruction and the target instruction identified by the forward branch target address). Instructions within the predicted instruction sequence which may already have been fetched prior to predicting the branch instruction taken may be retained within the pipeline of the processor, and yet subsequent instructions may be fetched.

David B. Witt

Papers

High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations

Data cache which speculatively updates a predicted data cache storage location with store data and subsequently corrects mispredicted updates

System for store to load forwarding of individual bytes from separate store buffer entries to form a single load word

Superscalar microprocessor employing a data cache capable of performing store accesses in a single clock cycle

Processor configured to selectively cancel instructions from its pipeline responsive to a predicted-taken short forward branch instruction