In general, techniques are described for configuring and managing virtual networks. For example, a distributed virtual network controller is described that configures and manages an overlay network within a physical network formed by plurality of switches. A plurality of servers are interconnected by the switch fabric, each of the servers comprising an operating environment executing one or more virtual machines in communication via the overlay networks. The servers comprises a set of virtual switches that extends the overlay network as a virtual network to the operating environment of the virtual machines. The controller may instruct the servers and the virtual switches to perform various operations, such as determining a physical network path taken by packets of a network packet flow, determining latency through the network, re-routing traffic in the virtual network due to network events, replicating traffic for multicasting, providing multi-tenant services to support multiple virtual networks, monitoring and logging traffic characteristics within the virtual networks and other operations.

Physical path determination for virtual network packet flows

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.

Method and apparatus for shared I/O in a load/store fabric

Methods and apparatus, including computer program products, implementing techniques for forming an Advanced Switching (AS) packet by applying AS path binding information to a packet received over a Peripheral Component Interconnect-Express (PCIe) fabric according to a downstream port identifier associated with the packet, and sending the AS packet to an AS fabric. Methods and apparatus, including computer program products, implementing techniques for processing an AS packet received over an AS fabric by comparing an AS payload of the AS packet with one or more memory spaces associated with port identifiers, determining whether the AS payload comprises a base packet to be transmitted to the PCIe fabric based on the comparison, and if so, removing an AS header from the AS packet to reveal the base packet.

Packet processing in switched fabric networks

Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.

Electronic device and method for fabricating the same

With processor and memory technologies pushing the performance limit, the bottleneck is clearly shifting towards the system interconnect. Any solution that addresses the PCI bus-based interconnect, which has serious scalability problems, must also protect the huge legacy infrastructure. PCI Express provides such an evolutionary approach and allows a smooth migration towards building a highly scalable next generation interconnect. Advanced switching further boosts the capabilities of PCI Express by allowing a rich application space to be covered that includes multiprocessing and peer-to-peer communication. Indeed, the synergy between PCI Express and advanced switching permits the adoption of an evolutionary yet revolutionary approach for building the interconnect of the future.

PCI express and advanced switching: evolutionary path to building next generation interconnects

Described is an aggregation device comprising a plurality of virtual network interface cards (vNICs) and an input/output (I/O) processing complex. The vNICs are in communication with a plurality of processing devices. Each processing device has at least one virtual machine (VM). The I/O processing complex is between the vNICs and at least one physical NIC. The I/O processing complex includes at least one proxy NIC and a virtual switch. The virtual switch exchanges data with a processing device of the plurality of processing devices via a communication path established by a vNIC of the plurality of vNICs between the at least one VM and at least one proxy NIC.

Systems and methods for input/output virtualization

Described are systems and methods for interconnecting devices. A switch fabric is in communication with a plurality of electronic devices. A rendezvous memory is in communication with the switch fabric. Data is transferred to the rendezvous memory from a first electronic device of the plurality of electronic devices in response to a determination that the data is ready for output from a memory at the first electronic device and in response to a location allocated in the rendezvous memory for the data.

Server node interconnect devices and methods

Described are systems and methods for communication between a plurality of electronic devices and an aggregation device. An aggregation device processes instructions related to a configuration of an electronic device in communication with the aggregation device. One or more virtual devices are generated in response to processing the instructions. The electronic device enumerates a configuration space to determine devices for use by the electronic device. The aggregation device detects an access of the configuration space by the electronic device. The one or more virtual devices are presented from the aggregation device to the electronic device in accordance with the instructions.

Systems and methods for sharing devices in a virtualization environment

Even though there is a commonality in their physical and link layers, Advanced Switching (AS) is more than merely an extension of PCI Express. The role of PCI Express is primarily as a chip-interconnect. In contrast, AS functions as a true system fabric interconnect encompassing domains that are vastly different and indeed more sophisticated than that of PCI Express’. In such a setup, congestion management is crucial for optimal utilization of the fabric bandwidth. Congestion control in network fabrics has generally been based on end-to-end and link-by-link schemes for controlling packet injection. Though seemingly adequate, these schemes may not be effective in handling “transient” congestion arising from intermittent traffic − for transient congestion can indeed occur in fabrics operating well below their saturation limit. In such scenarios, a link-by-link scheme does not prevent congestion from spreading while an end-to-end scheme may result in under-utilization of the fabric bandwidth. This paper details a congestion control mechanism called Status Based Flow Control (SBFC) that has been incorporated into AS and is specifically targeted for alleviating the transition congestion problem. The SBFC mechanism exploits the source-based path routing used in AS. It enables upstream switch nodes to modify the transmission of packets based on the congestion status of links in a downstream switch. Simulation studies show that the SBFC mechanism indeed permits optimal usage of the fabric bandwidth during periods of transient congestion and effectively complements the traditional end-to-end and link-by-link schemes for congestion control.

David E. Mayhew

Papers

PCI express and advanced switching: evolutionary path to building next generation interconnects

Systems and methods for input/output virtualization

Server node interconnect devices and methods

Systems and methods for sharing devices in a virtualization environment

A Localized Congestion Control Mechanism for PCI Express Advanced Switching Fabrics