Showing papers by "David Z. Pan published in 1999"

Buffer block planning for interconnect-driven floorplanning

Abstract: This paper studies buffer block planning for interconnect-driven floorplanning in deep submicron designs. We first introduce the concept of feasible region (FR) for buffer insertion, and derive closed-form formula for FR. We observe that the FR for a buffer is quite large in general even under fairly tight delay constraint. Therefore, FR gives us a lot of flexibility to plan for buffer locations. We then develop an effective buffer block planning (BBP) algorithm to perform buffer clustering such that the overall chip area and the buffer block number can be minimized. To the best of our knowledge, this is the first in-depth study on buffer planning for interconnect-driven floorplanning with both area and delay consideration.

Interconnect delay estimation models for synthesis and design planning

Abstract: In this paper we develop a set of interconnect delay estimation models with consideration of various layout optimizations, including optimal wire-sizing (OWS), simultaneous driver and wire sizing (SDWS), and simultaneous buffer insertion/sizing and wire sizing (BISWS). These models have been tested on a wide range of parameters and shown to have about 90% accuracy on average compared with those from running complex optimization algorithms directly followed by HSPICE simulations. Moreover, our models run in constant time in practice. As a result, these simple, fast, yet accurate models are expected to be very useful for a wide variety of purposes, including layout-driven logic and high level synthesis, performance-driven floorplanning, and interconnect planning.

Interconnect estimation and planning for deep submicron designs

Abstract: This paper reports two sets of important results in our exploration of an interconnect-centric design flow for deep submicron (DSM) designs: (i) We obtain efficient yet accurate wiring area estimation models for optimal wire sizing (OWS). We also propose a simple metric to guide area-efficient performance optimization; (ii) Guided by our interconnect estimation models, we study the interconnect architecture planning problem for wire-width designs. We achieve a rather surprising result which suggests that two pre-determined wire widths per metal layer are sufficient to achieve near-optimal performance. This result will greatly simplify the routing architecture and tools for DSM designs. We believe that our interconnect estimation and planning results will have a significant impact on DSM designs.