A double gated structure of Gate-Stack Doping-Less Tunnel Field Effect Transistor (GS-DLTFET) is proposed in this paper. Source and Drain regions of the FET are not doped using the charge plasma concept, which makes the device free from the random dopant fluctuation issue. A multi-layer structure is formed on the gate by imposing the layers of dielectrics. The device thus formed is analyzed by various parameters i.e., performing the AC and DC simulations on the device and studying the drain current characteristics of the device. One of the important factor i.e., effect of temperature variations are also seen on the various parameters of the device. The analyzed results are compared with the Doping-Less Tunnel Field Effect Transistor (DLTFET) and found to be better in performance. SILVACO ATLAS device simulator software has been used to carry out the simulations of the proposed device for analyzing the device performance.

Study of DC and AC characteristics of gate-stack doping-less tunnel FET

In this paper, a Gate-stack Doping-less Tunnel field effect transistor is proposed using a double- gate doping-less TFET(DLTFET) with a multilayer gate-stack architecture. The device characteristics are demonstrated and compared with DLTFET. It is found that the proposed architecture is having better performance than DLTFET. It is based on Charge plasma concept. There is no Source and Drain doping applied. Thus, it is free from Random dopant fluctuation issue and highly reliable. The gate dielectrics are used in stack manner to form a multilayer architecture. It provides the ON current of about 0.1 mA/µm with a low OFF current, 5×10 -18 A/µm. The threshold voltage is 0.8V and the Sub-threshold swing is calculated as 77mV/dec. All the simulations has been performed using SILVACO ATLAS device simulator.

Deepali Vasnik

Papers

Design and analysis of gate-stack doping-less tunnel field effect transistor