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Design and analysis of gate-stack doping-less tunnel field effect transistor

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TLDR
In this paper, a gate-stack DNTFET with a multilayer gate stack architecture is proposed, which is based on charge plasma concept and free from random dopant fluctuation issue and highly reliable.
Abstract
In this paper, a Gate-stack Doping-less Tunnel field effect transistor is proposed using a double- gate doping-less TFET(DLTFET) with a multilayer gate-stack architecture. The device characteristics are demonstrated and compared with DLTFET. It is found that the proposed architecture is having better performance than DLTFET. It is based on Charge plasma concept. There is no Source and Drain doping applied. Thus, it is free from Random dopant fluctuation issue and highly reliable. The gate dielectrics are used in stack manner to form a multilayer architecture. It provides the ON current of about 0.1 mA/µm with a low OFF current, 5×10 -18 A/µm. The threshold voltage is 0.8V and the Sub-threshold swing is calculated as 77mV/dec. All the simulations has been performed using SILVACO ATLAS device simulator.

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Proceedings ArticleDOI

Study of DC and AC characteristics of gate-stack doping-less tunnel FET

TL;DR: In this article, a double gated structure of Gate-Stack Doping-Less Tunnel Field Effect Transistor (GS-DLTFET) is proposed, which makes the device free from the random dopant fluctuation issue.
References
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Book ChapterDOI

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Journal ArticleDOI

Tunnel field-effect transistors as energy-efficient electronic switches

TL;DR: Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Journal ArticleDOI

Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec

TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Journal ArticleDOI

Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric

TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI

Band-to-band tunneling in carbon nanotube field-effect transistors.

TL;DR: How the structure of the nanotube is the key enabler of this particular one-dimensional tunneling effect is discussed, which is controlled here by the valence and conduction band edges in a bandpass-filter-like arrangement.
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