The present invention is a graphical user interface in a computing device having a processor running an operating system and a display. The graphical user interface comprises a touch screen and a driver coupling the touch screen to the operating system. The driver can display a plurality of icons on the touch screen, or a plurality of screen images having at least one icon, with each of the icons associated with operations on the display and/or the touch screen. Other embodiments include the touch screen having unactivated and activated states, as well as the presence of an application programming interface that enables an application to display at least one image on the touch screen.

Touch screen with user interface enhancement

The present invention utilizes an aggregator for searching, packaging and delivering content. The aggregator processes requests, searches, provides search results and acquires content. The aggregator, operating in a communications network, includes a request and results processing server, a search engine server coupled to the request and results processing server and a content acquisition server coupled to the request and results processing server. A request and results processing server receives a request for content, the search engine server searches for the content and the content acquisition program acquires content for delivery to the user. The request and results processing server includes a search request processor that receives information related to a user's search request and provides the information to a search results form builder that creates an electronic search request.

Video and digital multimedia aggregator

A method and an apparatus are used to target interactive virtual objects to subscribers in a television delivery system. Programs are selected and virtual object locations are defined in the selected programs. The virtual objects (1265) available for targeting categorized and categories are correlated to subscriber information (1210) to determine the optimum targeting of the virtual objects (1260). The virtual objects may be targeted (1220) based on individual subscriber information (1210) or on information related to a group of subscribers. When a frame of program includes a virtual object location, a default or an alternate virtual objects is displayed. The virtual object location may change over space or time. The virtual object may be interactive, and may be used to link a subscriber to a remote location, such as an Internet web site. The television terminals record which virtual objects were displayed and report this information back to the headends and the operations center. The reported information is used to generate billing for commercial advertisers and to analyze viewer watching habits.

Method and apparatus for targeting of interactive virtual objects

A program guide in which a video layer includes a plurality of video objects including title objects, each title object having associated with it a channel and at least one time slot, the video layer being formed in response to a received video stream; and a graphics layer comprising a plurality of graphics objects including title overlay objects, each of the title overlay objects selectively imparting at least a visual de-emphasis to a respective title object in the video layer, the visual de-emphasis being imparted to title objects not being associated with a desired time slot.

Data structure and methods for providing an interactive program guide

A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple graphics layers, and the processing elements process two or more graphics layers in parallel to generate blended graphics. Alpha values may be used while blending graphics. The processing elements may be integrated on an integrated circuit chip with an input for receiving the graphics data and other video and graphics components. The display engine may also include a graphics controller for receiving two or more graphics layers in parallel, for arranging the graphics layers in an order suitable for parallel processing, and for providing the arranged graphics layers to the processing elements. The blended graphics may be blended with HDTV video or SDTV video, which may be extracted from compressed data streams such as an MPEG Transport stream.

Video and graphics system with parallel processing of graphics windows

Disclosed is a digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals. This is accomplished with a minimum of DRAM demand through the use of a Spill Buffer.

Memory management for an MPEG2 compliant decoder

An integrated digital video system is configured to implement picture-in-picture merging of video signals from two or more video sources, as well as selective overlaying of on-screen display graphics onto the resultant merged signal. The picture-in-picture signal is produced for display by a television system otherwise lacking picture-in-picture capability. The digital video system can be implemented, for example, as an integrated decode system within a digital video set-top box or a digital video disc player. In one implementation, a decompressed digital video signal is downscaled and merged with an uncompressed video signal to produce the multi-screen display. The uncompressed video signal can comprise either analog or digital video. OSD graphics can be combined within the integrated system with the resultant multi-screen display or only with a received uncompressed analog video signal.

Integrated video processing system having multiple video sources and implementing picture-in-picture with on-screen display graphics

An address generation engine is disclosed for a digital video decoder unit coupled to memory in a digital video decoder system wherein the memory accommodates multi-format and/or reduced video data storage. The address generation engine includes a processor and address generation hardware. The processor, coupled to access encoded data to be decoded by the digital video decoder unit, has microcode for deriving from the encoded data relative location information including a vertical component and a horizontal component. The address generation hardware includes a row address register and a column address register for receiving the vertical component and horizontal component, respectively, derived by the processor. The address generation hardware is configured for generating from the vertical component and the horizontal component either a macroblock write address for writing a reconstructed macroblock of data to memory, a motion compensation read address for accessing pertinent motion vector information of the encoded data for reconstructing the macroblock, and a pan and scan offset address usable by a display unit for displaying reconstructed video data in pan and scan format.

Multi-format reduced memory MPEG decoder with hybrid memory address generation

A digital video decoder system, method and article of manufacture are provided having integrated scaling capabilities for presentation of video in full size or a predetermined reduced size, while at the same time allowing for reduced external memory requirements for frame buffer storage. The integrated system utilizes an existing decimation unit to scale the decoded stream of video data when the system is in scaled video mode. Display mode switch logic oversees switching between normal video mode and scaled video mode, wherein the switching occurs without perceptual degradation of a display of the decoded stream of video data. Scaled decoded video frames are buffered in a frame buffer which is partitioned depending upon whether the digital video decoding system is in normal video mode or scaled video mode. In scaled video mode, the frame buffer accommodates both full size I and P frames, as well as scaled I, P & B frames. The full size I and P frames are used to support future decode operations, while the scaled I, P & B frames are retrieved for display.

MPEG video decoder with integrated scaling and display functions

Trick mode playback is implemented by disengaging a frame synchronization signal, and then decoding “I” and “P” frames to two (or more) buffers. Specifically, each buffer has a pointer that is associated with a memory/origin address. The pointers are locked in place by disengaging the frame synchronization signal. Once the pointers are locked in place, the “I” frames and “P” frames are decoded to the two buffers in an alternating fashion based on a continuous swapping of the memory addresses associated with the two pointers. Because both “I” and “P” frames (as opposed to only “I” frames) are decoded and displayed, the trick mode playback appears smoother. In addition, because the frame synchronization signal was disengaged, the frames can be decoded at a rate faster than a single frame time. That is, one frame need not be completely decoded and read out before the next frame is decoded.

Dennis P. Cheney

Papers

Memory management for an MPEG2 compliant decoder

Integrated video processing system having multiple video sources and implementing picture-in-picture with on-screen display graphics

Multi-format reduced memory MPEG decoder with hybrid memory address generation

MPEG video decoder with integrated scaling and display functions

MPEG-2 decoder, method and buffer scheme for providing enhanced trick mode playback of a video stream