To evaluate the promise of potential computing technologies, this review examines a wide range of fundamental limits, such as to performance, power consumption, size and cost, from the device level to the system level. Computers have evolved at a remarkable rate, with improvements over the past fifty years roughly in line with Gordon Moore's prescient observation that the number of transistors in a dense integrated circuit would double approximately every two years. The rate of 'Moore scaling' is slowing down and other physical limits are looming, but new technologies such as carbon nanotubes, graphene and quantum computation are on the way. In this Review, Igor Markov takes a fresh look at the fundamental limits at various levels, from devices to complete systems, and compares loose and tight limits. Markov argues that the study of the limits of fundamental limits to computation can lead to new insights for emerging technologies. An indispensable part of our personal and working lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the past fifty years. Such Moore scaling now requires ever-increasing efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and increase our understanding of integrated-circuit scaling, here I review fundamental limits to computation in the areas of manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, I recapitulate how some limits were circumvented, and compare loose and tight limits. Engineering difficulties encountered by emerging technologies may indicate yet unknown limits.

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Limits on fundamental limits to computation

Deep neural networks offer considerable potential across a range of applications, from advanced manufacturing to autonomous cars. A clear trend in deep neural networks is the exponential growth of network size and the associated increases in computational complexity and memory consumption. However, the performance and energy efficiency of edge inference, in which the inference (the application of a trained network to new data) is performed locally on embedded platforms that have limited area and power budget, is bounded by technology scaling. Here we analyse recent data and show that there are increasing gaps between the computational complexity and energy efficiency required by data scientists and the hardware capacity made available by hardware architects. We then discuss various architecture and algorithm innovations that could help to bridge the gaps. This Perspective highlights the existence of gaps between the computational complexity and energy efficiency required for the continued scaling of deep neural networks and the hardware capacity actually available with current CMOS technology scaling, in situations where edge inference is required; it then discusses various architecture and algorithm innovations that could help to bridge these gaps.

Scaling for edge inference of deep neural networks

Due to the breakdown of Dennardian scaling, the percentage of a silicon chip that can switch at full frequency is dropping exponentially with each process generation. This utilization wall forces designers to ensure that, at any point in time, large fractions of their chips are effectively dark or dim silicon, i.e., either idle or significantly underclocked. As exponentially larger fractions of a chip's transistors become dark, silicon area becomes an exponentially cheaper resource relative to power and energy consumption. This shift is driving a new class of architectural techniques that “spend” area to “buy” energy efficiency. All of these techniques seek to introduce new forms of heterogeneity into the computational stack. We envision that ultimately we will see widespread use of specialized architectures that leverage these techniques in order to attain orders-of-magnitude improvements in energy efficiency. However, many of these approaches also suffer from massive increases in complexity. As a result, we will need to look towards developing pervasively specialized architectures that insulate the hardware designer and the programmer from the underlying complexity of such systems. In this paper, I discuss four key approaches — the four horsemen — that have emerged as top contenders for thriving in the dark silicon age. Each class carries with its virtues deep-seated restrictions that requires a careful understanding of the underlying tradeoffs and benefits.

Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse

Moore's Law will continue providing abundance of transistors for integration, only to be limited by the energy consumption. Near threshold voltage (NTV) operation has potential to improve energy efficiency by an order of magnitude. We discuss design techniques necessary for reliable operation over a wide range of supply voltage — from nominal down to subthreshold region. The system designed for NTV can dynamically select modes of operation, from high performance, to high energy efficiency, to the lowest power.

Near-threshold voltage (NTV) design: opportunities and challenges

Current trends in technology scaling foreshadow worsening transistor reliability as well as greater numbers of transistors in each system. The combination of these factors will soon make long-term product reliability extremely difficult in complex modern systems such as systems on a chip (SoC) and chip multiprocessor (CMP) designs, where even a single device failure can cause fatal system errors. Resiliency to device failure will be a necessary condition at future technology nodes. In this work, we present a network-on-chip (NoC) routing algorithm to boost the robustness in interconnect networks, by reconfiguring them to avoid faulty components while maintaining connectivity and correct operation. This distributed algorithm can be implemented in hardware with less than 300 gates per network router. Experimental results over a broad range of 2D-mesh and 2D-torus networks demonstrate 99.99% reliability on average when 10% of the interconnect links have failed.

/pdf/a-highly-resilient-routing-algorithm-for-fault-tolerant-nocs-1qdnexuo6z.pdf

A highly resilient routing algorithm for fault-tolerant NoCs

Power has become the primary design constraint for chip designers today. While Moore's law continues to provide additional transistors, power budgets have begun to prohibit those devices from actually being used. To reduce energy consumption, voltage scaling techniques have proved a popular technique with subthreshold design representing the endpoint of voltage scaling. Although it is extremely energy efficient, subthreshold design has been relegated to niche markets due to its major performance penalties. This paper defines and explores near-threshold computing (NTC), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors. This region retains much of the energy savings of subthreshold operation with more favor- able performance and variability characteristics. This makes it applicable to a broad range of power-constrained computing segments from sensors to high performance servers. This paper explores the barriers to the widespread adoption of NTC and describes current work aimed at overcoming these obstacles.

Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits Future computer systems promise to achieve an energy reduction of 100 or more times with memory design, device structure, device fabrication techniques, and clocking, all optimized for low-voltage operation.

failure mechanisms, suchastimedependent dielectrice breakdown, electromigration, andthermal cycling havebecome a . keyconcern inprocessor design. Thetraditional approach toreli- X ability qualification assumes that theprocessor will operate atmaxi-V|; mumperformance continuously under worst casevoltage andtem- Typical perature conditions. However, thetypical processor spends avery small fraction ofitsoperational time atmaximumvoltage andtem- perature. Inthis paper, weshowhowthis results inareliability Time(years) - 10 "slack" that canbeleveraged toprovide increased performance dur- ingperiods ofpeak processor demand. Wedevelop anovel, real time Figure 1.Reliability degradation overtime. reliability modelbased onworkload driven conditions. We then Inthis paper, wepropose theuseofso-called dynamic reliability propose anewdynamic reliability management (DRM)scheme that management (DRM), where real-time workloads andthermal infor- results in20-35% performance improvement during periods ofpeak mation provides accurate inputs toreliability models forprojecting computational demand while ensuring therequired reliability life-thedegradation caused byvarious failure mechanisms. Thepro- time. jected failure probability isused tocontrol themaximum voltage in thedynamic voltage scaling (DVS)algorithm. C.8 (ategories)n Subjormanet ade.Ritors Theconcept ofDRM ismotivated inFigure 1.Theline labeled worst-case shows accumulated damage duetoafailure mechanism, GeneralTerms:Management, Reliability, Design, Perform- such asoxide breakdown, over a10-year time span under worst-case ance conditions. Theaccumulated damage fromtypical processor usage traces isshownbytheline labeled typical andresults inmuchlower

http://ieeexplore.ieee.org/iel5/11109/35624/01688955.pdf

Reliability Modeling andManagement inDynamic Microprocessor-Based Systems

An improved reference current generator is provided. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The result is a power efficient, temperature compensated reference current generator.

A low power reference current generator with tunable temperature sensitivity

http://ma.ecsdl.org/content/MA2007-01/6/379.full.pdf

Design of Hybrid Implantable Power Systems (HIPS): Optimization Based on Fundamentals of Materials and Energetics

Miniature wireless sensors with long lifetimes enable new applications for medical diagnosis, infrastructure monitoring, military surveillance, and environmental sensing among many other applications in a growing field. Sensor miniaturization leads to decreased on-sensor energy capacity, and lifetime requirements further constrain the sensor's power budget. To enable millimeter-scale wireless sensors with life- times of months to years, a new class of low-power circuit techniques is required. Wireless sensors collect and digitize environmental data before processing and transmitting the data wirelessly to base stations or other sensor nodes. Recent low-power advances for each of these functions shed light on how ubiquitous sensing can become a reality.

Circuit Design Advances for Wireless Sensing Applications Many recent designs for miniature, millimeter-scale, long-lifetime, ultralow-power wireless sensors are described with applications in areas such as medical diagnosis, infrastructure monitoring, and environmental sensing.

Dennis Sylvester

Papers

Reliability Modeling andManagement inDynamic Microprocessor-Based Systems

A low power reference current generator with tunable temperature sensitivity

Design of Hybrid Implantable Power Systems (HIPS): Optimization Based on Fundamentals of Materials and Energetics

Circuit Design Advances for Wireless Sensing Applications Many recent designs for miniature, millimeter-scale, long-lifetime, ultralow-power wireless sensors are described with applications in areas such as medical diagnosis, infrastructure monitoring, and environmental sensing.