A programmable logic device is provided that contains circuitry that may be used for observing logic signals from programmable logic circuits on the device for testing the operation of the device. Circuitry is also provided that may be used for preloading data into various circuits on the device. The logic signal observing circuitry may allow registered signals to be observed, may allow combinatorial signals to be observed, or may allow both registered and combinatorial signals to be observed.

Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits

In a user-configurable integrated circuit including a plurality of uncommitted conductors which may be programmably connected to one another and to functional circuit blocks by a user to form electronic circuits, apparatus for testing for defects in the form of breaks in the electrical continuity of individual ones of the conductors prior to formation of the electronic circuits by a user, including circuitry responsive to external signals for temporarily connecting together selected ones of the uncommitted conductors to form a series circuit having a first end conductor and a second end conductor, circuitry for placing an electrical charge on the first end conductor such that a selected dynamic voltage is placed on the first end conductor, circuitry for driving the second end conductor to a voltage different from the selected dynamic voltage, circuitry for sensing the voltage on the first end conductor at a predetermined time after the driving voltage has been removed, circuitry for storing a signal related to the sensed voltage on the first end conductor, and circuitry for communicating the signal to an input/output pad of the integrated circuit.

Testability architecture and techniques for programmable interconnect architecture

A scannable latch system comprises a plurality of scannable latches and clock driver circuit that allow at-speed testing of integrated circuits. Each scannable latch comprises a master latch, a slave latch and an auxiliary latch. The master latch is a two input latch capable of receiving data from two sources. The output of the master latch is coupled to the input of the slave and auxiliary latches. The clock driver circuitry receives a clock and control signals which are transformed into signals that operate the scannable latch in three different modes. In the normal mode, the slave latch is transparent and the data is held primarily in the master latch. In the scan mode, data may be shifted into the master, shifted out through the auxiliary latch, or shifted both in and out with a propagate function. Finally, in a test mode independent data values may be stored in the master latch and the slave latch.

Scannable latch system and method

The present invention discloses an apparatus for controlling and observing test data stored in scannable-D-flip-flops independent of a system clock, thereby making the scannable-D-flip-flops well suited for partial scanning Design-For-Test (DFT) techniques. Under the present invention, the scannable-D-flip-flop is comprised of two master latches and one slave latch such that the scannable-D-flip-flops may operate in a normal mode of operation or a scan/test mode of operation. During normal mode of operation, the first master latch operates together with the slave latch in response to the system clock. During the scan/test mode of operation, the second master latch operates together with the slave latch in response to a scan clock. Since the scanning of external test data is controlled by the scan clock, the conventional non-scannable D-flip-flops in the design, which are controlled by the system clock, maintain their previous states during a scanning operation. Also disclosed is a method for performance testing integrated circuits utilizing the scanning application of the scannable-D-flip-flops. This is accomplished by constructing a test circuit that spans the entire silicon die area. By using a special AC-TEST-MODE control signal, the scannable D-flip-flops are set to a "flow-through" mode to provide a direct path through the scannable flip-flops such that the test circuit forms an oscillator in which the frequency of the device can be measured.

Apparatus for scannable D-flip-flop which scans test data independent of the system clock

A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.

Enhanced test circuit

This application describes a peripheral cell structure for VLSI chips that requires the use of standard cells having both input and output capability connected to nearly all of the signal carrying pins. The cells function is alterable (to input or output and to where the data input signals originate) by control signals which may originate with a control register. The clock input signal is split into two independent signals to selectively disable the input or output registers, thus allowing the control register to be changed without affecting the contents of the other two registers. An early signal is also provided to prepare for mode changes.

Flexible VLSI on-chip maintenance and test system with unit I/O cell design

This application teaches that more accurate measurements of clock skew can be had by providing a clock monitor pin directly connected to the clock bus internal to the VLSI chip.

Clock monitor for use with vlsi chips

PURPOSE: To improve testability by removing a pin connected for receiving a system clock input, and providing a pin electrically connected with a system clock bus. CONSTITUTION: A unit I/O cell design arranged in the periphery connected with each signal pin P constructing serially connected input register and output register, and an additional register flip flop 21 are provided on a serial path. Then, the input of each pin P connected with the unit I/O cell is buffered by an input buffer IB, and the communication of all normal functions for an outside world is operated through those unit I/O cells. Therefore, input and output can be operated by all the signal pins P before the designer of an integrated circuit for specific use can start the work, so that system design can be easily attained. Thus, the testability of the integrated circuit can be improved.

Very large scale integrated circuit chip with clock monitor

A VLSI chip has a core logic area with a system 
clock bus CLB to distribute clock signals to the 
application specific logic in that area. Clock signals 
are supplied to the bus via one pin P3, and clock skew 
(clock pulse distribution delay) is monitored by means 
of a second pin (P4) connected (at 49) to a point on the 
bus separated from the connection point of the first 
pin. Substantially all normal (operational) signals to 
and from the core logic area are coupled to the chip 
pins by means of input/output cells located in the 
peripheral area of the chip.

Clock distribution on vlsi chip

A VLSI chip has a core logic area surrounded by a peripheral zone including a plurality of 1/0 cells (10) through which nearly all signals between the pins and the core logic (CLI, CLO) pass. Each cell has an input buffer (IB) and an output buffer (OB) through which signals pass respectively from pin to core logic and vice versa, and a control register controlling the operation of the I/O cells. Two shift registers, an input register and an output register, are formed by flip-flops also included in the I/O cells and connected to the buffers, core logic, and pins, and to test data in and out registers and pins. Some of the I/O cells may be dummy cells forming part of the input and/or output registers but not having pins. Timing circuitry (MS1, MS2; 52, 53) provides early signals (TST EARLY, TCE EARLY) to set up predetermined flip-flops prior to their receiving clocked signals (TST COPY, TCE COPY), and for separating a system clock input (CLKO) as a first clock signal (CLK1) to the control circuitry and a second clock signal (CLK2) to the input and output registers to allow the control register to operate without clocking the input or output registers.

Don Adorian Daane

Papers

Flexible VLSI on-chip maintenance and test system with unit I/O cell design

Clock monitor for use with vlsi chips

Very large scale integrated circuit chip with clock monitor

Clock distribution on vlsi chip

VLSI chip with test circuitry