A VLSI chip has a core logic area with a system 
clock bus CLB to distribute clock signals to the 
application specific logic in that area. Clock signals 
are supplied to the bus via one pin P3, and clock skew 
(clock pulse distribution delay) is monitored by means 
of a second pin (P4) connected (at 49) to a point on the 
bus separated from the connection point of the first 
pin. Substantially all normal (operational) signals to 
and from the core logic area are coupled to the chip 
pins by means of input/output cells located in the 
peripheral area of the chip.

ON CHIP CLOCK SKEW CONTROL METHOD AND APPARATUS ABSTRACT OF THE DISCLOSURE A master clock signal, used to operate the clock devices (e.g., flip flops) formed on an integrated circuit chip, includes first and second clock paths. The first clock path is a linear trunk having laterally extending tributaries. The clock trunk is driven, through buffer circuits, at both ends with the master clock, and the internal devices coupled to the tributaries to receive the clock signal. The second path comprises a closed loop formed proximate the periphery of the integrated circuit chip. Clock buffer circuitry receives the master clock signal and apply that master clock signal to two points on the closed loop path. The closed loop path is used to communicate the master clock to only the input/output devices, i.e., those that receive data and/or informational signals from an external source, or those communicate such signals to a destination external to the integrated circuit.

Clock distribution on vlsi chip

On chip clock skew control method and apparatus

A VLSI integrated circuit chip (10) includes integral test circuitry formed on the chip. The test circuitry includes a shift register (20) comprising a plurality of latches located adjacent the input/output pads (14) of the chip (10). Control circuitry (18) is included which causes test data to be serially entered into the shift register (20) and then clocked into the internal circuit (12) of the chip (10) in order to test the chip operation. The output signals generated by the internal circuit (12) in response to the test signals are transferred to the shift register (20). The contents of the shift register (20) are then serially shifted out of the device and may be compared with desired results in order to determine whether or not the chip (10) is operating properly. The inclusion of the circuitry greatly reduces the number of pads (14) which must be contacted to test the chip (10).

Vlsi chip with integral testing circuit

An AC test is disclosed which measures a time from the application of an input pulse on an input terminal of a circuit under consideration to the appearance of an output pulse on an output terminal of the circuit. The input terminal of the circuit is connected with an input driver through a first relay and connected with a pulse generator through a second relay. The opening-closing sequence of the first and second relays is selected such that the input terminal of the circuit is connected with at least one of the pulse generator and the input driver during a status setting of the circuit and during the application of the pulse. As a result, the occurrence of noises at the time of change-over operation between the pulse generator and the input driver is suppressed.

Clock distribution on vlsi chip

Citations

On chip clock skew control method and apparatus

References

Vlsi chip with integral testing circuit

Method of testing pulse delay time

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