A method and circuitry are provided for current input analog to digital conversion. A current input (14) is conducted through an input path. The current input is directed through a plurality of current paths (30a-d). A current through each current path (30a-d) is compared against an associated reference current (36a-d), and a respective output signal (34a-d) indicative thereof is output, such that the respective output signals (34a-d) are indicative of a magnitude of the current input (14).

Circuitry and method for current input analog to digital conversion

A subranging analog-to-digital converter is disclosed having digitally controlled subranging for eliminating switching gain and switching paths in the analog section thereof. The digitally controlled subranging apparatus may be applied to either a single time-shared quantizer embodiment or a converter embodiment including a plurality of simultaneously operated quantizers. In either case, the conversion is formed in a series of quantizer operations on a sampled analog signal input for forming a final accumulated digital word conversion representative thereof. Another aspect of the present invention includes the addition of apparatus in a subranging A/D converter for maintaining the pre-alignment of the various conversion dynamic subranges thereof. In this aspect, the subranges of the converter are prealigned to affect a unique set of digital conversion codes of subranged conversions of the analog signal input value corresponding to the conversion threshold transition regions between the pre-aligned subranges. An anomaly in the digital conversion codes of said analog signal input value is detected and used to govern the adjustment of the conversion dynamic range of at least one of the quantizers of the converter in order to ameliorate the anomalous condition.

A/D converter having digitally controlled subranging and self-alignment apparatus for use therein

The set/reset latch circuit comprises a multi-level differential cascode current switch (DCCS) tree (11) operable to develop set and reset control pulses in response to logic input signals, a constant current source (10) two load resistors (14-L, 14-R), a bistable device (12) comprising a cross-coupled pairs of transistors and switching from a first state to a second state in response to respectively to the set and reset control pulses. The DCCS tree (11) includes means (16) for connecting the current source (10) to the bistable device (12) selectively through one of two different serial current paths of the tree (11) to provide a current to one of the load resistors (14-L, 14-R) through one of the cross coupled pair of transistors to hold the bistable device in one state in the absence of the set and reset control pulses.

Latch circuit with differential cascode current switch logic

A subranging analog to digital converter (ADC). The ADC (200) includes a novel resistive ladder (56) for a differential quantizer (50) and a novel summing node circuit (150). The novel resistive ladder (56) includes an input terminal (52), a plurality of serially connected resistors R coupled to the input terminal (52), and a pair of complementary current sources (66 and 68) for maintaining a constant current flow through the ladder (56). The novel summing node circuit (150) includes an input terminal (152) for receiving an input signal, a pair of complementary DACs (156 and 158) for generating a reconstruction signal, and a summing amplifier (164) for subtracting the reconstruction signal from the input signal to produce a residue signal. The invention also includes a method for trimming the subranging ADC. The novel method (250) includes the steps of trimming the complementary current sources of the coarse quantizer to match each other (252), trimming each of the DAC cells on one of the complementary DACs (254), trimming the overall DAC gain to match the gain of the coarse quantizer (256); and trimming the gain of the fine quantizer to match one coarse quantization Q level (260).

Resistive ladder, summing node circuit, and trimming method for a subranging analog to digital converter

An analog-to-digital converter including a reference voltage generator for generating coarse and fine reference voltages, a first group of comparators for comparing an analog input voltage with the coarse reference voltages, a second group of comparators and an encoder for encoding outputs of the comparators. The fine reference voltages and the analog input voltage are applied to a plurality of differential amplifiers which are organized into an odd number of groups, each group including an equal number of differential amplifiers. First outputs as well as second outputs of corresponding differential amplifiers of each groups are respectively added to each other. This added first and second output signals are respectively delivered to the second group of comparators. Outputs of the second groups of comparators are selectively inverted based on the outputs of the first group of comparators, thereby the most significant bits (MSB) and the least significant bits (LSB) are obtained in parallel.

Analog-to-digital converter

A window comparator latch network is disclosed for track or sampling a differential input signal and for "latching" the input signal upon a clock signal. Several latch networks are disclosed for both single and dual differential input configurations. The dual input configuration includes first and second pairs of differential transistors which are coupled to a differential regenerative and latching pair of transistors. The regenerative and latching transistor pair provides an output signal having first or second states only upon the required clock signal being applied to a current switching transistor pair. Negative differential signals applied to both first and second pairs of differential transistors results in a "0" logic state output signal from the regenerative and latching transistors. A positive differential signal results in a logic "1" output state. Positive input signals applied to both differential transistors results in a logic "0" output state. Thus the latch network provides a "window" output signal.

High speed latching comparator

A quantizer network is disclosed for decoding an analog signal and providing a four-bit digital output. The analog input signal is divided or quantized into sixteen discrete voltage ranges and applied to sixteen differential amplifiers. Each amplifier has a different reference which must be exceeded before it provides an output signal. The sixteen differential amplifiers are connected to nine latch networks which respond to the signals from the amplifiers and provide a cyclic code in response thereto. The latch networks are connected to a network of logic gates which decode the cycle code into a four-bit digital output signal. The output signals from the logic gate network are applied to output stages which extend the valid time of the output signal from the logic gates.

Don C. Devendorf

Papers

High speed latching comparator

Analog to digital converter utilizing a quantizer network

Analog-Digital-Umsetzer