Showing papers by "Dong Xiang published in 2003"

Nonscan design for testability for synchronous sequential circuits based on conflict resolution

Abstract: A testability measure called conflict, based on conflict analysis in the process of sequential circuit test generation is introduced to guide nonscan design for testability. The testability measure indicates the number of potential conflicts to occur or the number of clock cycles required to detect a fault. A new testability structure is proposed to insert control points by switching the extra inputs to primary inputs, using whichever extra inputs of all control points can be controlled by independent signals. The proposed design for testability approach is economical in delay, area, and pin overheads. The nonscan design for testability method based on the conflict measure can reduce many potential backtracks and make many hard-to-detect faults easy-to-detect; therefore, it can enhance actual testability of the circuit greatly. Extensive experimental results are presented to demonstrate the effectiveness of the method.

Reliable broadcasting in wormhole-routed hypercube-connected networks using local safety information

Abstract: This paper presents a method to cope with reliable broadcasting in faulty hypercubes using local safety information. A new definition, broadcast subcube, is introduced, with which various techniques are proposed to improve performance of the broadcast algorithm. Local safety information is well used in the fault-tolerant broadcast algorithm by considering only safety of the broadcast subcube. An unsafe hypercube can be split into a set of maximal safe subcubes. If these maximal safe subcubes meet certain requirements (listed in this paper), then broadcasting can still be done successfully and, in some cases, optimal broadcast is still possible. The sufficient condition for optimal broadcast of a message is presented in an unsafe hypercube. Extensive simulation results show that the proposed method outperforms previous methods, in all cases.

Cost-effective scan architecture and a test application scheme for scan testing with non-scan test power and test application cost

Abstract: A method and apparatus for scan design architecture with non-scan testing cost is disclosed. In one embodiment, the method comprises: transforming a plurality of sequential cells for a sequential circuit to a plurality of controllable and observable cells for a combinational circuit; connecting said plurality of sequential cells with at least one shifter registers; obtaining at least one scan chains; and substituting the ATPG step for said sequential circuit with the ATPG for said combinational circuit. In another embodiment, the apparatus comprises: means for transforming a plurality of sequential cells for a sequential circuit to a plurality of controllable and observable cells for a combinational circuit; means for connecting said plurality of sequential cells with at least one shifter registers; means for obtaining at least one scan chains; and means for substituting the ATPG step for said sequential circuit with the ATPG for said combinational circuit.

Improving test quality of scan-based BIST by scan chain partitioning

Abstract: The test effectiveness of a test-per-scan BIST scheme is highly dependent on the length and the number of the scan chains. Fewer cycles are adopted to capture test responses when the length of the scan chains increases. On the other hand, the number of test inputs should be increased when the number of the scan chains increases. Another important feature of the test-per-scan BIST scheme is that test responses of the circuit at the inputs of the scan flip-flops are unobservable during the shift cycles. A new scan architecture is proposed to make a scan-based circuit more observable. The scan chain is partitioned into multiple segments, according to which multiple capture cycles can be inserted to receive test responses during the shift cycles based on the test-per-scan test scheme. This scheme directly makes the circuit more observable and testable. Unlike other BIST schemes using multiple capture cycles after the shift cycles, our method inserts multiple capture cycles inside the shift cycles, but not after the shift cycles. Sufficient experimental results are presented to demonstrate the effectiveness of the method.

Local-Safety-Information-Based Fault-Tolerant Broadcasting in Hypercubes

Abstract: This paper presents a method for fault-tolerant broadcasting in faulty hypercubes using a new metric called local safety. A new concept of the broadcast subcube is introduced, based on which various techniques are proposed to improve the performance of a broadcast algorithm. An unsafe hypercube can be split into a set of maximal safe sub-cubes. We show that if these maximal safe subcubes meet certain requirements given in the paper, broadcasting can still be carried out successfully, and in some cases optimal broadcast is still possible. The sufficient condition for optimal broadcasting is also presented. Limited backtracks are utilized in the process of broadcasting by setting up a partial broadcast tree. Extensive simulation results are presented.

Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis

Abstract: A two stage non-scan design for testability method is proposed. The first stage selects test points based on an earlier testability measure conflict. A new design for testability algorithm is proposed to select test points by a fault-oriented testability measure conflict+ in the second stage. Test points are selected in the second stage based on the hard faults after the initial ATPG run of the design for testability circuit in the preliminary stage. The new testability measure conflict+ based on conflict analysis of hard-faults in the process of test generation is introduced, which emulates most general features of sequential ATPG. The new testability measure reduces testability of a fault to the minimum D or D̄ controllability of the primary outputs, and therefore, does not need observability measure any more. Effective approximate schemes are adopted to get reasonable estimation of the testability measure. A couple of effective techniques are also adopted to accelerate the process of the proposed design for testability algorithm. Experimental results show that the proposed method gets even better results than two of the recent non-scan design for testability methods nscan and lcdft. key words: at-speed test, conflict, containing assignment, nonscan design for testability, sequential depth for testability

Non-scan design for testability for mixed RTL circuits with both data paths and controller via conflict analysis

Abstract: A non-scan design for testability method for RTL circuits based on conflict analysis is proposed. Conflict analysis is presented based on a new 5-valued system to estimate testability of data paths. New test point structures for RTL circuit design for testability are introduced. Nonscan design for testability is proposed based on conflict resolution. Unlike most of the previous methods, our method considers testability of data paths and the controller simultaneously. Different classes of test points can be inserted into data paths and the controller. Intensive techniques are presented to connect extra inputs of test points with PI ports, which avoids generating reconvergent fanouts that cause new conflicts.