IEEE International Solid-State Circuits Conference

sultinanimplementation thatcannotbeexecuted within Multimedia applications usually havethroughput constraints. these timing constraints. Itisnecessary totakethetiming An implementation mustmeetthese constraints, while it constraints intoaccount while minimizing thebuffers. Sevminimizes resource usageandenergyconsumption. The eralapproaches havebeenproposed forminimizing buffer computeintensive kernels oftheseapplications areoften requirements underathroughput constraint. In[9], atechspecified asSynchronous Dataflow Graphs.Communica- nique basedonlinear programming isproposed tocalculate tionbetween nodesinthesegraphs requires storage space aschedule thatrealizes themaximalthroughput whileit whichinfluences throughput. We present exacttechniquestries tominimize buffer sizes. Hwangetal.propose aheuristochart thePareto spaceofthroughput andstorage trade- ticthatcantakeresource constraints into account [10]. This offs, whichcanbeusedtodetermine theminimal storage methodistargeted towards a-cyclic graphs anditalways spaceneeded toexecute agraphunderagiven throughputmaximizes throughput rather thanusing athroughput conconstraint. Thefeasibility oftheapproach isdemonstratedstraint. Thus,itcouldleadtoadditional resource requirewithanumberofexamples. ments. In[13], buffer minimization formaximal throughput ofa subclass ofSDFGs(homogeneous SDFGs) isachieved Categories andSubject Descriptors: C.3[Special-pur- viaaninteger linear programming approach. Ingeneral, poseandApplication-based Systems] Signal processing sys- theminimal buffer sizes obtained withthisapproach cantems notbetranslated toexact minimal buffer sizes forarbitrary GeneralTerms:Algorithms, Experimentation, Theory. SDFGs.We propose, incontrast toexisting work, an ex

Exploring Trade-Offs inBuffer Requirements and Throughput Constraints forSynchronous Dataflow Graphs*

In the past few years, MPSoC has become the most popular solution for embedded computing. However, the challenge of programming MPSoCs also comes as the biggest side-effect of the solution. Especially, when designers have to face the legacy C code accumulated through the years, the tool support is mostly unsatisfactory. In this paper, we propose an integrated framework, MAPS, which aims at parallelizing C applications for MPSoC platforms. It extracts coarse-grained parallelism on a novel granularity level. A set of tools have been developed for the framework. We will introduce the major components and their functionalities. Two case studies will be given, which demonstrate the use of MAPS on two different kinds of applications. In both cases the proposed framework helps the programmer to extract parallelism efficiently.

MAPS: an integrated framework for MPSoC application parallelization

A video bit allocation technique adopting a visual distortion sensitivity model for better rate-visual distortion coding control is proposed in this paper. Instead of applying complicated semantic understanding, the proposed automatic distortion sensitivity analysis process analyzes both the motion and the texture structures in the video sequences in order to achieve better bit allocation for rate-constrained video coding. The proposed technique evaluates the perceptual distortion sensitivity on a macroblock basis, and allocates fewer bits to regions permitting large perceptual distortions for rate reduction. The proposed algorithm can be incorporated into existing video coding rate control schemes to achieve same visual quality at reduced bitrate. Experiments based on H.264 JM7.6 show that this technique achieves bit-rate saving of up to 40.61%. However, the conducted subjective viewing experiments show that there is no perceptual quality degradation. EDICS-1-CPRS, 3-QUAL.

https://ir.nctu.edu.tw:443/bitstream/11536/12640/1/000234850000002.pdf

Visual sensitivity guided bit allocation for video coding

The present invention provides a large format fingerprint capture apparatus, system and method that is low power, compact, and lightweight and has a platen area greater than 3.0 square inches. The present system is typically powered, controlled, and exchanges data over a single data/control/power connection to a host PC, e.g., a desk top computer, PDA, or laptop computer although the system can also be used in a wireless fashion with a power subsystem so no physical connections are required. In a preferred embodiment the large format fingerprint device is directly connected to a completely disconnected portable PC, such as a laptop having only a battery power source. The primary system components of the present invention combine to minimize power, size and weight and, thus, enhance portability and battery life. The system typically includes a light source, a prism, a camera (including the lens), and a case. Optional elements comprise holographic elements such as gratings and holographic optical elements (HOEs), a battery subsystem, magnetic stripe reader, barcode reader, platen heater, platen blower, and mirrors to divert the image beam.

Low power fingerprint capture system, apparatus, and method

This paper presents a Multiprocessor System-on-Chips (MPSoC) architecture used as an execution platform for the new C-language based MPSoC design framework we are currently developing. The MPSoC architecture is based on an existing SoC platform with a commercial RISC core acting as the host CPU. We extend the existing SoC with a multiprocessor-array block that is used as the main engine to run parallel applications modeled in our design framework. Utilizing several optimizations provided by our compiler, an efficient inter-communication between processing elements with minimum overhead is implemented. A host-interface is designed to integrate the existing RISC core to the multiprocessor-array. The experimental results show that an efficacious integration is achieved, proving that the designed communication module can be used to efficiently incorporate off-the-shelf processors as a processing element for MPSoC architectures designed using our framework.

A Multiprocessor SoC Architecture with Efficient Communication Infrastructure and Advanced Compiler Support for Easy Application Development

Speaker recognition is a biometric technique which uses individual speakers voice samples as a input for recognition purpose. Main goal of this work is to obtain better accuracy for speaker recognition system for large number of voice database. In this paper, a comparative study is made between various combinations of features for speaker identification system with feedforward artificial neural network(FFANN) and support vector machine for 10 and 20 speakers. Linear predictive coding, Mel frequency cepstral coefficient and zero crossing rate are used as a feature extraction techniques. Each features are tested separately and in combination with FFANN and SVM classifier on Matlab software. For ANN classifier 70% of total database are used for training,15% for validation and remaining 15% data are used for testing, number of hidden layers and number of neurons used are 2 and 80 respectively. It is observed from the result that efficiency of the system is not dropping by increasing number of speakers from 10(320 voice samples) to 20(640 voice samples) when using combination of LPC, MFCC, ZCR features with ANN classifier.

Speaker Recognition Using LPC, MFCC, ZCR Features with ANN and SVM Classifier for Large Input Database

While Multiprocessor System-On-Chips (MPSoCs) are becoming widely adopted in embedded systems, there is a strong need for methodologies that quickly and accurately estimate performance of such complex systems. In this paper, we present a novel method for accurately estimating the cycle counts of parameterized MPSoC architectures through workload simulation driven by program execution traces encoded in the form of branch bitstreams. Experimental results show that the proposed method delivers a speedup factor of 70.15 to 238.58 against the instruction-set simulator based method while achieving high cycle accuracy whose estimation error ranges between 0.016% and 0.459%.

Trace-driven workload simulation method for Multiprocessor System-On-Chips

A simple extension used to assist the decomposition of task-level concurrency within C programs is presented in this paper. The concurrency decomposition is meant to be used as the point of entry for Multiprocessor System-on-Chips (MPSoC) architectures' design-flow. Our methodology allows the (re)use of readily available reference C programs and enables easy and rapid exploration for various alternatives of task partitioning strategies; a crucial task that greatly influences the overall quality of the designed MPSoC. A test case using a JPEG encoder application has been performed and the results are presented in this paper.

Decomposition of Task-Level Concurrency on C Programs Applied to the Design of Multiprocessor SoC

The performance of an fingerprint authentication algorithm can be decreased significantly if the fingerprint image has lots of broken ridges caused by cutline, or the overlap area between the template and input is very small. For the purpose of these specific kinds of verification, a Scale Invariant Feature Transformation (SIFT) feature-based algorithm for fingerprint verification is presented. This approach is not based on traditional minutiae or ridge features. The SIFT keypoints in Gaussian scale-space and the local descriptor for each SIFT keypoint can be extracted by using this method. The verification is done by matching the descriptor, which is invariant to image scale and rotation. In this paper a proper pre-processing is carried out on the fingerprint image instead of using the original fingerprint image. This can make the algorithm adaptive to the variation of the impression condition. Furthermore, a Hough transform adapted to fingerprint verification is performed rather than only using SIFT keypoint descriptor matching. The fusion with minutiae information is also applied for efficiency and accuracy. Two specific databases are captured for experiments. Experiment results of proposed algorithm on specific databases show significant improvement compared with common minutiae-based method. Experiment results on FVC2002 Database show that Equal Error Rate (EER) and False Matching Rate (FMR) of our proposed algorithm can be decreased to about 20% of previous SIFT-based works.

Dongju Li

Papers

A Multiprocessor SoC Architecture with Efficient Communication Infrastructure and Advanced Compiler Support for Easy Application Development

Speaker Recognition Using LPC, MFCC, ZCR Features with ANN and SVM Classifier for Large Input Database

Trace-driven workload simulation method for Multiprocessor System-On-Chips

Decomposition of Task-Level Concurrency on C Programs Applied to the Design of Multiprocessor SoC

Adaptive SIFT-Based Algorithm for Specific Fingerprint Verification