D
Douglas W. Stout
Researcher at IBM
Publications - 50
Citations - 1514
Douglas W. Stout is an academic researcher from IBM. The author has contributed to research in topics: Integrated circuit & Dropout voltage. The author has an hindex of 17, co-authored 50 publications receiving 1513 citations. Previous affiliations of Douglas W. Stout include GlobalFoundries.
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Patent
Electrostatic discharge protective circuit of triple well semiconductor device
James P. Pequignot,Jeffrey H. Sloan,H Baldeman Stephen,Douglas W. Stout,ジェームス・ピー・ペクイノット,ジェフリー・エイチ・スローン,スティーブン・エイチ・ボールドマン,ダグラス・ダブリュ・スタウト +7 more
TL;DR: In this paper, a tri-well diode junction is constructed on an area where the p-region 6 is adjacent to the regions 3, the region 3A, and the region 8.
Patent
Dual rail power supply sequence tolerant off-chip driver
TL;DR: In this paper, the authors proposed a protection circuit for indeterminate logic levels caused by loss of one of the power supplies in a two-power-supply CMOS integrated circuit.
Patent
Method and apparatus for storing circuit calibration information
TL;DR: In this paper, a method for altering circuit characteristics to make them independent of processing parameters of devices within an integrated circuit is disclosed, where a process parameter is measured by a kerf or on-chip built-in test on a selective set of chip on a wafer, and the results are stored on a storage device within each respective chip.
Patent
Design structure for implementing oxide leakage based voltage divider network for integrated circuit devices
TL;DR: In this paper, a design structure embodied in a machine readable medium used in a design process includes a voltage divider device, including a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region; the first and second gates configured to have an input voltage coupled thereacross; and at least one of a source of the FET and a drain of a FET configured to having an output voltage taken therefrom.
Patent
High performance state saving circuit
TL;DR: In this article, a state saving circuit includes a state-saving latch powered by an uninterruptible power supply, and a cut-off control device that selectively connects the state saving latch to a pair of latch nodes based upon a control signal.