In this paper, the parallel COrdinate Rotation DIgital Computer (CORDIC) rotation algorithm in circular and hyperbolic coordinate is proposed. The most critical path of the conventional CORDIC rotation lies in the determination of rotation directions, which depends on the sign of the remaining angle after each iteration. Using the binary-to-bipolar recoding (BBR) and microrotation angle recoding techniques, the rotation directions can be predicted directly from the binary value of the initial input angle. The original sequential CORDIC rotations can be divided into two phases where the rotations in each phase can be executed in parallel. Our proposed architectures have a more regular and simpler prediction scheme compared to previous approaches. The critical path delay is reduced since the concurrently predicted rotations can be combined using multioperand carry-save addition structures.

Para-CORDIC: parallel CORDIC rotation algorithm

The fast Fourier transform (FFT) is a very important algorithm in digital signal processing. The locally pipelined (LPPL) architecture is an efficient structure for FFT processor designing in a real-time embedded system. Two basic building blocks, to the LPPL FFT processor, the butterfly in pipeline, and address generating, are discussed in this brief. Based on the "deep" feedback to butterfly-2, a novel approach for pipelined architecture, the radix-2 single-path deep delay feedback architecture is proposed. For length-N discrete Fourier transform computation, the dominant hardware requirements are minimal for complex multipliers log/sub 4/N-1 and adders 2log/sub 4/N. As an integral need of the LPPL FFT processor design, address generating and coefficient store-load structures are also presented.

An efficient locally pipelined FFT processor

A computationally efficient and high-quality preserving discrete cosine transform (DCT) architecture is presented. It is obtained by optimising the Loeffler DCT based on the coordinate rotation digital computer (Cordic) algorithm. The computational complexity is reduced significantly from 11 multiply and 29 add operations (Loeffler DCT) to 38 add and 16 shift operations (i.e. similar to the complexity of the binDCT) without losing quality. After synthesising with TSMC 0.13-mum technology library, Synopsys PrimePower was used to estimate the power consumption at gate-level. The experimental results show that the proposed 8-point one-dimensional DCT architecture only consumes 19% of the area and about 16% of the power of the original Loeffler DCT. Moreover, it also retains the good transformation quality of the original Loeffler DCT. In this regard, the proposed Cordic-based Loeffler DCT is very suitable for low-power and high-quality encoder/decoders (codecs) used in battery-based systems.

Low-power and high-quality Cordic-based Loeffler DCT for signal processing

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Applications of digital signal processing

An efficient implementation of discrete cosine transform (DCT) computations are presented based on the so-called shifted discrete Fourier transform (SDFT), a generalization of the conventional DFT (DFT). Due to the simple form of the factorized matrices, the derived architecture can be easily constructed from the cascade of only two types of parameterized hardware modules: butterfly operators and rotators. The butterfly operator performs the conventional butterfly shuffling and addition/subtraction. The rotator that performs plane rotations of two-dimensional (2-D) vectors is designed using carry-save-adder (CSA)-based unfolded pipelined CORDIC architecture where the rotation angles can be approximated with different accuracies using a sequence of bipolar signs. The proposed one-dimensional and 2-D DCT implementations composed of the above two types of parameterized modules can be used as flexible and reusable Silicon Intellectual Property (SIP) for the DCT computation unit to be embedded in system-on-a-chip (SoC) design. The proposed implementations have many features and advantages, including SIP reusability, low complexity, high-throughput, regularity, scalability (easy extension of transform length), and flexibility (approximated DCT with various accuracies).

Efficient VLSI implementations of fast multiplierless approximated DCT using parameterized hardware modules for silicon intellectual property design

This paper presents an efficient approach for computing the N-point (N=2/sup n/) scaled discrete cosine transform (DCT) with the coordinate rotation digital computer (CORDIC) algorithm. The proposed algorithm is based on an indirect approach for computing the DCT so that the vector rotations are completely separated from the other operations and placed at the end of the DCT unit. As a result, unlike the other CORDIC-based DCT architectures, the proposed scaled DCT architecture does not require scale factor compensation. The number of CORDIC iterations is minimized through the optimal angle recoding method based on the three-value CORDIC algorithm. Although this three-value CORDIC algorithm results in different scale factors for different angles, this does not incur any extra hardware in the proposed scaled DCT architecture.

A scaled DCT architecture with the CORDIC algorithm

This paper presents an efficient pipelined architecture for the N/sup m/-point m-dimensional discrete Fourier transform (DFT). By using a two-level index mapping scheme that is different from the conventional decimation-in-time (DIT) or decimation-infrequency (DIF) algorithms, the conventional pipelined architecture for the one-dimensional (1-D) fast Fourier transform (FFT) can be efficiently used for the computation of higher dimensional DFTs. Compared with systolic architectures, the proposed scheme is area-efficient since the computational elements (CEs) use the minimum number of multipliers, and the number of CEs increases only linearly with respect to the dimension m. It can be easily extended to the N/sup m/-point m-dimensional DFT with large m and/or N, and it is more flexible since the throughput can be easily varied to accommodate various area/throughput requirements.

A pipelined architecture for the multidimensional DFT

This paper presents a new pipelined architecture for the N/sup m/-point FFT (Fast Fourier Transform). Unlike conventional pipelined architectures, which are based on the DIT (Decimation in Time) or DIF (Decimation in Frequency) algorithms, the proposed architecture is based on a new index mapping scheme which has two levels of decomposition. As a result, the new architecture can be efficiently used to realize a pipelined implementation of the N/sup m/-point m-dimensional DFT simply by omitting some of the twiddle factor ROMs.

E.E. Swartzlander

Papers

A scaled DCT architecture with the CORDIC algorithm

A pipelined architecture for the multidimensional DFT

A new pipelined implementation of the fast Fourier transform