Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to an undesirably large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, the important concept of controlling horizontal leakage through vertical structures is highlighted. Several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design. The concept of vertical doping engineering can also be realized in bulk Si to obtain good subthreshold characteristics without large junction capacitance or heavy channel doping. >

Scaling the Si MOSFET: from bulk to SOI to bulk

A characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data. The physical causes of mismatch are discussed in detail for both p- and n-channel devices. Statistical methods are used to develop analytical models that relate the mismatch to the device dimensions. It is shown that these models are valid for small-geometry devices only. Extensive experimental data from a 3-/spl mu/m CMOS process are used to verify the models. The application of the transistor matching studies to the design of a high-performance digital-to-analog converter (DAC) is discussed. A circuit design methodology is presented that highlights the close interaction between the circuit yield and the matching accuracy of devices. It has been possible to achieve a circuit yield of greater than 97% as a result of the knowledge generated regarding the matching behavior of transistors and due to the systematic design approach.

Characterisation and modeling of mismatch in MOS transistors for precision analog design

A functional MOS transistor is proposed which works more intelligently than a mere switching device. The functional transistor calculates the weighted sum of all input signals at the gate level, and controls the 'on' and 'off' of the transistor based on the result of such a weighted sum operation. Since the function is quite analogous to that of biological neurons, the device is named a neuron MOSFET, or neuMOS (vMOS). The device is composed of a floating gate and multiples of input gates that capacitively interact with the floating gate. As the gate-level sum operation is performed in a voltage mode utilizing the capacitive coupling effect, essentially no power dissipation occurs in the calculation, making the device ideal for ULSI implementation. The basic characteristics of neuron MOSFETs as well as of simple circuit blocks are analyzed based on a simple transistor model and experiments. Making use of its very powerful function, a number of interesting circuit applications are explored. A soft hardware logic circuit implemented by neuMOS transistors is also proposed. >

A functional MOS transistor featuring gate-level weighted sum and threshold operations

A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness t/sub si/; gate oxide thickness t/sub ox/) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 mu m while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator. >

Scaling theory for double-gate SOI MOSFET's

The threshold voltage, V/sub th/, of lightly doped drain (LDD) and non-LDD MOSFETs with effective channel lengths down to the deep-submicrometer range has been investigated. Experimental data show that in the very-short-channel-length range, the previously reported exponential dependence on channel length and the linear dependence on drain voltage no longer hold true. A simple quasi-two-dimensional model is used, taking into account the effects of gate oxide thickness, source/drain junction depth, and channel doping, to describe the accelerated V/sub th/ on channel length due to their lower drain-substrate junction built-in potentials. LDD devices also show less V/sub th/ dependence on drain voltage because the LDD region reduces the effective drain voltage. Based on consideration of the short-channel effects, the minimum acceptable length is determined. >

Threshold voltage model for deep-submicrometer MOSFETs

As MOSFET dimensions are reduced, lower voltages, shallower junctions, thinner oxides, and heavier doping help to maintain long-channel behavior. A simple, empirical relation has been found between these parameters and the minimum channel length for which long-channel subthreshold behavior will be observed. This approximate relation provides an estimate for MOSFET parameters not requiring reduction of all dimensions by the same scale factor.

Generalized guide for MOSFET miniaturization

As MOSFET dimensions are reduced, it is desirable to preserve long-channel MOSFET behavior. In general, lower voltages, shallower junctions, thinner oxides, and heavier doping help to maintain long-channel behavior as channel length is reduced. Our purpose here is to propose a simple, approximate relation between these parameters and the minimum channel length for which long-channel subthreshold behavior will be observed. This relation provides a simple estimate for MOSFET parameters, not requiring reduction of all dimensions by the same scale factor.

E.H. Nicollian

Papers

Generalized guide for MOSFET miniaturization

Generalized guide for MOSFET miniaturization