This paper presents a low offset voltage, low noise dynamic latched comparator using a self-calibrating technique. The new calibration technique does not require any amplifiers for the offset voltage cancellation and quiescent current. It achieves low offset voltage of 1.69 mV at 1 sigma in low power consumption, while 13.7 mV is measured without calibration. Furthermore the proposed comparator requires only one phase clock while conventionally two phase clocks were required leading to relaxed clock. Moreover, a low input noise of 0.6 mV at 1 sigma, three times lower than the conventional one, is obtained. Prototype comparators are realized in 90 nm 10M1P CMOS technology. Experimental and simulated results show that the comparator achieves 1.69 mV offset at 250 MHz operating, while dissipating 40 muW/GHz ( 20 fJ/conv. ) from a 1.0 V supply.

A low-noise self-calibrating dynamic comparator for high-speed ADCs

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115×225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step.

/pdf/a-10-bit-charge-redistribution-adc-consuming-1-9-mu-w-at-1-4cww0cq029.pdf

A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$ W at 1 MS/s

The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double-tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. Post-layout simulation results in a 0.18- μm CMOS technology confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 2.5 and 1.1 GHz at supply voltages of 1.2 and 0.6 V, while consuming 1.4 mW and 153 μW, respectively. The standard deviation of the input-referred offset is 7.8 mV at 1.2 V supply.

/pdf/analysis-and-design-of-a-low-voltage-low-power-double-tail-wi7aqv7w29.pdf

Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator

An ADC for energy scavenging is proposed using a charge-redistribution DAC, a dynamic 2-stage comparator, and a delay-line-based controller realized in CMOS. The charge-redistribution DAC can be used in a simple way to make a SAR ADC. The 10b differential ADC uses bootstrapped NMOS devices to sample the differential input voltage onto two identical charge-redistribution DACs. The test chip is fabricated in a 65nm CMOS process. In this ADC, the MSB is set in between the sampling phase and the first comparison, saving energy and time.

/pdf/a-1-9mw-4-4fj-conversion-step-10b-1ms-s-charge-208y5x3yg8.pdf

A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC

Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption However, the increased severity of manufacturing-induced parameter variations at lower voltages limits voltage scaling to a minimum voltage, Vccmin, below which a processor cannot operate reliably Memory cell failures in large memory structures (eg, caches) typically determine the Vccmin for the whole processor Memory failures can be persistent (ie, failures at time zero which cause yield loss) or non-persistent (eg, soft errors or erratic bit failures) Both types of failures increase as supply voltage decreases and both need to be addressed to achieve reliable operation at low voltages In this paper, we propose a novel adaptive technique to improve cache lifetime reliability and enable low voltage operation This technique, multi-bit segmented ECC (MS-ECC) addresses both persistent and non-persistent failures Like previous work on mitigating persistent failures, MS-ECC trades off cache capacity for lower voltages However, unlike previous schemes, MS-ECC does not rely on testing to identify and isolate defective bits, and therefore enables error tolerance for non-persistent failures like erratic bits and soft errors at low voltages Furthermore, MS-ECC's design can allow the operating system to adaptively change the cache size and ECC capability to adjust to system operating conditions Compared to current designs with single-bit correction, the most aggressive implementation for MS-ECC enables a 30% reduction in supply voltage, reducing power by 71% and energy per instruction by 42%

/pdf/improving-cache-lifetime-reliability-at-ultra-low-voltages-4lxbh5lyb8.pdf

Improving cache lifetime reliability at ultra-low voltages

A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a 1-sigma offset of 8mV, the circuit consumes 92fJ/decision with a 1.2V supply. It has an input equivalent noise of 1.5mV and requires 18ps setup-plus-hold time

/pdf/a-double-tail-latch-type-voltage-sense-amplifier-with-18ps-aluyuprtro.pdf

E. Kiumperink

Papers

A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time