A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage. This separation enables fast operation over a wide common-mode and supply voltage range. With a 1-sigma offset of 8mV, the circuit consumes 92fJ/decision with a 1.2V supply. It has an input equivalent noise of 1.5mV and requires 18ps setup-plus-hold time

/pdf/a-double-tail-latch-type-voltage-sense-amplifier-with-18ps-aluyuprtro.pdf

A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time

A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preamplifier to improve the conversion speed. Measurement results on a 90 nm CMOS prototype operated at 1.2 V supply show 3 mW total power consumption with a peak SNDR of 56.6 dB and a FOM of 77 fJ/conv-step.

/pdf/a-10-bit-100-ms-s-reference-free-sar-adc-in-90-nm-cmos-4b9jo24381.pdf

A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

This paper describes the design and optimization of VCOs with quadrature outputs. Systematic design of fully integrated LC-VCOs with a high inductance tank leads to a cross-coupled double core LC-VCO as the optimal solution in terms of power consumption. Furthermore, a novel fully differential frequency tuning concept is introduced to ease high integration. The concepts are verified with a 0.25-/spl mu/m standard CMOS fully integrated quadrature VCO for zero- or low-IF DCS1800, DECT, or GSM receivers. At 2.5-V power supply voltage and a total power dissipation of 20 mW, the quadrature VCO features a worst-case phase noise of -143 dBc/Hz at 3-MHz frequency offset over the tuning range. The oscillator is tuned from 1.71 to 1.99 GHz through a differential nMOS/pMOS varactor input.

/pdf/low-power-low-phase-noise-differentially-tuned-quadrature-q31y9qihqr.pdf

Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS

This paper presents a low offset voltage, low noise dynamic latched comparator using a self-calibrating technique. The new calibration technique does not require any amplifiers for the offset voltage cancellation and quiescent current. It achieves low offset voltage of 1.69 mV at 1 sigma in low power consumption, while 13.7 mV is measured without calibration. Furthermore the proposed comparator requires only one phase clock while conventionally two phase clocks were required leading to relaxed clock. Moreover, a low input noise of 0.6 mV at 1 sigma, three times lower than the conventional one, is obtained. Prototype comparators are realized in 90 nm 10M1P CMOS technology. Experimental and simulated results show that the comparator achieves 1.69 mV offset at 250 MHz operating, while dissipating 40 muW/GHz ( 20 fJ/conv. ) from a 1.0 V supply.

A low-noise self-calibrating dynamic comparator for high-speed ADCs

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115×225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step.

/pdf/a-10-bit-charge-redistribution-adc-consuming-1-9-mu-w-at-1-4cww0cq029.pdf

A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$ W at 1 MS/s

An ADC for energy scavenging is proposed using a charge-redistribution DAC, a dynamic 2-stage comparator, and a delay-line-based controller realized in CMOS. The charge-redistribution DAC can be used in a simple way to make a SAR ADC. The 10b differential ADC uses bootstrapped NMOS devices to sample the differential input voltage onto two identical charge-redistribution DACs. The test chip is fabricated in a 65nm CMOS process. In this ADC, the MSB is set in between the sampling phase and the first comparison, saving energy and time.

/pdf/a-1-9mw-4-4fj-conversion-step-10b-1ms-s-charge-208y5x3yg8.pdf

A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC

"Switched Biasing" is proposed as a new circuit technique that exploits an intriguing physical effect: cycling a MOS transistor between strong inversion and accumulation reduces its intrinsic 1/f noise. The technique is implemented in a 0.8µm CMOS sawtooth oscillator by periodically off-switching of the bias currents during time intervals that they are not contributing to the circuit operation. Measurements show a reduction of the 1/f noise induced phase noise by more than 8 dB, while the power consumption is reduced by more than 30% as well.

/pdf/reducing-mosfet-1-f-noise-and-power-consumption-by-switched-4rlksm1x1t.pdf

Reducing MOSFET 1/f noise and power consumption by "Switched biasing"

This paper gives experimental proof of an intriguing physical effect: periodic on-off switching of MOS transistors in a CMOS ring oscillator reduces their intrinsic 1/f noise and hence the oscillator's close-in phase noise. More specifically, it is shown that the 1/f/sup 3/ phase noise is dependent on the gate-source voltage of the MOS transistors in the off state. Measurement results, corrected for waveform-dependent upconversion and effective bias, show an 8-dB-lower 1/f/sup 3/ phase noise than expected. It will be shown that this can be attributed to the intrinsic 1/f noise reduction effect due to periodic on-off switching.

/pdf/intrinsic-1-f-device-noise-reduction-and-its-effect-on-phase-2lzsias5na.pdf

Intrinsic 1/f device noise reduction and its effect on phase noise in CMOS ring oscillators

Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s.

/pdf/low-power-high-speed-transceivers-for-network-on-chip-vnbmbwvqy0.pdf

E. van Tuijl

Papers

A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time

A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC

Reducing MOSFET 1/f noise and power consumption by "Switched biasing"

Intrinsic 1/f device noise reduction and its effect on phase noise in CMOS ring oscillators

Low-Power, High-Speed Transceivers for Network-on-Chip Communication