When mirror-polished, flat, and clean wafers of almost any material are brought into contact at room temperature, they are locally attracted to each other by van der Waals forces and adhere or bond. This phenomenon is referred to as wafer bonding. The most prominent applications of wafer bonding are silicon-on-insulator (SOI) devices, silicon-based sensors and actuators, as well as optical devices. The basics of wafer-bonding technology are described, including microcleanroom approaches, prevention of interface bubbles, bonding of III-V compounds, low-temperature bonding, ultra-high vacuum bonding, thinning methods such as smart-cut procedures, and twist wafer bonding for compliant substrates. Wafer bonding allows a new degree of freedom in design and fabrication of material combinations that previously would have been excluded because these material combinations cannot be realized by the conventional approach of epitaxial growth.

Semiconductor wafer bonding

Silicon fusion and eutectic bonding processes based on the technique of localized heating have been successfully demonstrated. Phosphorus-doped polysilicon and gold films are applied separately in the silicon-to-glass fusion bonding and silicon-to-gold eutectic bonding experiments. These films are patterned as line-shape resistive heaters with widths of 5 or 7 /spl mu/m for the purpose of heating and bonding. In the experiments, silicon-to-glass fusion bonding and silicon to gold eutectic bonding are successfully achieved at temperatures above 1000/spl deg/C and 800/spl deg/C, respectively, by applying 1-MPa contact pressure. Both bonding processes can achieve bonding strength comparable to the fracture toughness of bulk silicon in less than 5 min. Without using global heating furnaces, localized bonding process is conducted in the common environment of room temperature and atmospheric pressure. Although these processes are accomplished within a confined bonding region and under high temperature, the substrate temperature remains low. This new class of bonding scheme has potential applications for microelectromechanical systems fabrication and packaging that require low-temperature processing at the wafer level, excellent bonding strength, and hermetic sealing characteristics.

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Localized silicon fusion and eutectic bonding for MEMS fabrication and packaging

An improved microelectromechanical device, such as a thermal ink jet die or printhead, is formed by the alignment of two planar substrates bonded together by an intermediate thick film layer of patterned polymeric material, such as polyimide. The improved device has a fully cured, patterned thick film layer which is planarized by chemical-mechanical polishing-to improve the bonding strength between the substrates. The planarization removes topographical formations generated during the deposition of the thick film layer and/or during the patterning of the recesses therein.

Micro-electromechanical die module with planarized thick film layer

In this report we describe a new way of fabricating integrated microfluidic elements in glass. By employing a matrix of underpinning posts and a thin wall, surrounding etched flow channels, an efficient sealing of glass chips substrates to thin cover glass can be accomplished. The use of this arrangement enables the overlay sheath of glass to hermetically close the flow channel by fusion bonding while avoiding problems with void or crack formation that are due to dust particles, non-planarity and differences in thermal coefficient of expansion. As an example a structure with a thin cover glass, useful for studying phenomena in capillary electrophoresis utilizing large numerical aperture microscope lenses, was fabricated.

https://iopscience.iop.org/article/10.1088/0960-1317/8/1/006/pdf

Method for fabrication of microfluidic systems in glass

Micromechanical smart sensor and actuator systems of high complexity become commercially viable when realized as a multi-wafer device in which the mechanical functions are distributed over different wafers and one of the wafers is dedicated to contain the readout circuits The individually-processed wafers can be assembled using wafer-to-wafer bonding and can be combined to one single functional electro-mechanical unit using through-wafer interconnect, provided that the processes involved comply with the constraints imposed by the proper operation of the active electrical and micromechanical subsystems This implies low-temperature wafer-to-wafer bonding and through-wafer interconnect Au/Si eutectic bonding has been investigated as it can conveniently be combined with bulk-micromachined through-wafer interconnect The temperature control in eutectic bonding has been shown to be critical

Low-temperature silicon wafer-to-wafer bonding using gold at eutectic temperature

The basic principles of wafer fusion bonding including pretreatment, room temperature mating, and thermal annealing are presented. Techniques for the characterization of the bond quality are reviewed. Results for fusion bonding of other materials such as silicon nitride and polysilicon are discussed with a view to bond quality and application. Examples of fusion processes for power device fabrication show the feasibility of the technique.

https://iopscience.iop.org/article/10.1088/0960-1317/2/3/001/pdf

Silicon fusion bonding and its characterization

The principles of the wafer fusion bonding technique at room temperature and with thermal treatment are described. Experiments using plain and patterned silicon wafers coated with different surface materials are presented. Results obtained for different thermal annealing conditions are discussed in terms of homogeneity and strength of the bond. Thinning of the bonded wafers is performed by grinding and polishing or with preferential etch techniques using p+ etchstops. Uniform silicon-on-insulator (SOI) films with thicknesses 1 mu m-30 mu m have been obtained.

https://iopscience.iop.org/article/10.1088/0960-1317/1/3/003/pdf

Wafer fusion bonding and its application to silicon-on-insulator fabrication

Intelligent power ICs are increasingly desired for applications in automotive electronics, motor control devices or flat panel displays. In order to meet the requirements regarding reliability, low area consumption and flexibility the dielectric isolation is superior to the other isolation techniques such as self isolation or junction isolation. Integrated power devices on fully isolated SOI wafers showed the advantages of bonded SOI material for this application. However, the full isolation restricts the power devices to area consuming lateral devices or up-drain DMOS type devices only suitable for medium power applications. Devices with high current and high breakdown voltage capability require vertical transistor types. So far, different attempts have been made to integrate vertical connected and dielectrically isolated areas on one wafer. We have developed a process, which allows the fabrication of vertical connected areas and device isolation before bonding and requires no special alignment. First, the area for the vertical contact is patterned and covered with a silicon nitride layer. Subsequently, V-grooves are patterned, etched and thermally oxidised. After removal of the nitride layer the V-grooves are filled with polysilicon. Depending on the deposition conditions, the vertical contact area is filled with polysilicon or epitaxial grown silicon. Thinning occurs by chemo-mechanical polishing. As in the "classical" DI process the oxide at the bottom of the V-groove serves as a polishing stop resulting in a better SOI thickness uniformity.

http://ieeexplore.ieee.org/iel3/4044/11594/00526505.pdf

Wafer bonding for intelligent power ICs: integration of vertical structures

Silicon-on-Insulator Films Obtained by Etchback of Bonded Wafers

Thermal bonding of oxidized wafers is used to produce dielectrically insulated silicon for device fabrication. The two step bonding process is described and experiments with different wafer surfaces including prestructured and nitride coated wafers are presented. Thinning techniques for Siliconon-Insulator (SOI) fabrication are compared regarding film uniformity and material quality. SOI films in the thickness of 1–10 microns have been obtained with an etchback process using a p+-etchstop layer.

E. Penteker

Papers

Silicon fusion bonding and its characterization

Wafer fusion bonding and its application to silicon-on-insulator fabrication

Wafer bonding for intelligent power ICs: integration of vertical structures

Silicon-on-Insulator Films Obtained by Etchback of Bonded Wafers

Wafer Bonding and Etchback Techniques for Silicon-on-Isulator Systems