We review work on In2O3:Sn films prepared by reactive e‐beam evaporation of In2O3 with up to 9 mol % SnO2 onto heated glass. These films have excellent spectrally selective properties when the deposition rate is ∼0.2 nm/s, the substrate temperature is ≳150 °C, and the oxygen pressure is ∼5×10−4 Torr. Optimized coatings have crystallite dimensions ≳50 nm and a C‐type rare‐earth oxide structure. We cover electromagnetic properties as recorded by spectrophotometry in the 0.2–50‐μm range, by X‐band microwave reflectance, and by dc electrical measurements. Hall‐effect data are included. An increase of the Sn content is shown to have several important effects: the semiconductor band gap is shifted towards the ultraviolet, the luminous transmittance remains high, the infrared reflectance increases to a high value beyond a certain wavelength which shifts towards the visible, phonon‐induced infrared absorption bands vanish, the microwave reflectance goes up, and the dc resisitivity drops to ∼2×10−4 Ω cm. The corre...

Evaporated Sn‐doped In2O3 films: Basic optical properties and applications to energy‐efficient windows

Modern computer microprocessor chips are marvels of engineering complexity. For the current 45 nm technology node, there may be nearly a billion transistors on a chip barely 1 cm2 and more than 10 000 m of wiring connecting and powering these devices distributed over 9-10 wiring levels. This represents quite an advance from the first INTEL 4004B microprocessor chip introduced in 1971 with 10 μm minimum dimensions and 2 300 transistors on the chip! It has been disclosed that advanced microprocessor chips at the 32 nm node will have more than 2 billion transistors.1 For instance, Figure 1 shows a sectional 3D image of a 90 nm IBM microprocessor, containing several hundred million integrated devices and 10 levels of interconnect wiring, designated as the back-end-of-the-line (BEOL). Since the invention of microprocessors, the number of active devices on a chip has been exponentially increasing, approximately doubling every two years. This trend was first described in 1965 by Gordon Moore,2 although the original discussion suggested doubling the number of devices every year, and the phenomenon became popularly known as Moore’s Law. This progress has proven remarkably resilient and has persisted for more than 50 years. The enabler that has permitted these advances is known as scaling, that is, the reduction of minimum device dimensions by lithographic advances (photoresists, tooling, and process integration optimization) by ∼30% for each device generation.3 It allowed more active devices to be incorporated in a given area and improved the operating characteristics of the individual transistors. It should be emphasized that the earlier improvements in chip performance were achieved with very few changes in the materials used in the construction of the chips themselves. The increase of performance with scaling * Corresponding author. E-mail: gdubois@us.ibm.com. † IBM Almaden Research Center. ‡ Stanford University. Willi Volksen received his B.S. in Chemistry (magna cum laude) from New Mexico Institute of Mining and Technology in 1972 and his Ph.D. in Chemistry/Polymer Science from the University of Massachusetts, Lowell, in 1975. He then joined the research group of Prof. Harry Gray/Dr. Alan Rembaum at the California Institute of Technology as a postdoctoral fellow and upon completion of the one-year appointment joined Dr. Rembaum at the Jet Propulsion Laboratory as a Senior Chemist in 1976. In 1977 Dr. Volksen joined the IBM Research Division at the IBM Almaden Research Center in San Jose, CA, where he is an active research staff member in the Advanced Materials Group of the Science and Technology function.

Low dielectric constant materials.

Electrical and optical properties of diamond-like carbon

Preparation and physical properties of transparent conducting oxide films

Atomic and subnanometer resolution in ambient conditions by atomic force microscopy

Fabrication of sharp silicon tips employing anisotropic wet etching and reactive ion etching

2D hexagonal patterns can be generated by the superimposition of two or three fringe patterns that have been formed by two-wave interference and that have rotations of 60° between them. Superimposing three exposures solves the problem of asymmetry in the cross section of structures, which is caused by double exposure. The resulting structure, however, depends on the phase shift of the third fringe pattern in relation to the previous two. We propose a method for controlling the phase shift, and we demonstrate that three different lattice geometries of hexagonal photonic crystals can be recorded when the phase is chosen.

https://www.repositorio.ufop.br/bitstream/123456789/1875/1/ARTIGO_RecordingDifferentGeometries.pdf

Edmundo da Silva Braga

Papers

Fabrication of sharp silicon tips employing anisotropic wet etching and reactive ion etching

Recording different geometries of 2D hexagonal photonic crystals by choosing the phase between two-beam interference exposures

Structural characterization of transparent semiconducting thin films of SnO2 and In2O3

Simulation of the enhancement factor from an individual 3D hemisphere-on-post field emitter by using finite elements method.

CF4 plasma etching of materials used in microelectronics manufacturing