A digital computer system includes a scalar CPU, a vector processor, and a shared cache memory. The scalar CPU has an execution unit, a memory management unit, and a cache controller unit. The execution unit generates load/store memory addresses for vector load/store instructions. The load/store addresses are translated by the memory management unit, and stored in a write buffer that is also used for buffering scalar write addresses and write data. The cache controller coordinates-loads and stores between the vector processor and the shared cache with scalar reads and writes to the cache. Preferably the cache controller permits scalar reads to precede scalar writes and vector load/stores by checking for conflicts with scalar writes and vector load/stores in the write queue, and also permits vector load/stores to precede vector operates by checking for conflicts with vector operate information stored in a vector register scoreboard. Preferably the cache controller includes vector logic which is responsive to vector information written in intra-processor registers by the execution unit. The vector logic keeps track of the vector length and blocks extra memory addresses generated by the execution unit for the vector elements. The vector logic also blocks the memory addresses of masked vector elements so that these addresses are not translated by the memory management unit.

Digital computer system with cache controller coordinating both vector and scalar operations

A random access memory having the capability to access one or more bytes in one or more memory word locations of a multi-byte memory array within one memory cycle. Variable length instruction and data words composed of multiple bytes are stored in a block of addressable locations in a memory so that individual bytes of each word are aligned in columns. Each column of bytes is addressable independently of the other byte columns via adders. A most significant bit portion of a memory location address is fed into a first input of column adders and the output of a first decoder circuit is fed into a second input of the adders for address incrementing within one memory cycle. A second decoder circuit generates a separate read or write enable line to each column of bytes. Both decoders are controlled by a least significant bit portion of the memory address and reference word byte size codes. A bi-directional multiplexer rearranges the order of the bytes so they appear in the proper order at the memory interface.

Byte addressable memory for variable length instructions and data

Disclosed is a memory system for reading and writing variable length data fields. Each of the data fields are addressed by the combination of a word address, a bit address, and a field length. Internal to the memory system, a total of 2N cells are addressed by each word address where N is the maximum field length. But only a portion of the addressed cells are selectively enabled in response to the bit address and field length. An N bit shifter right justifies the output data from the selectively enabled cells, and also realigns right justified input data to be written into the selectively enabled cells.

Bit addressable variable length memory system

Channel data buffer apparatus for buffering data being transferred between an input/output channel unit and a main storage unit in a digital data processing system. In the disclosed embodiment, data is generally transferred between the channel unit and the data buffer (a "channel/buffer" transfer) in two-byte segments and between the main storage unit and the data buffer (a "storage/buffer" transfer) in eight-byte segments. The data buffer is comprised of eight column-forming byte-wide multirow storage arrays each having its own address mechanism for accessing any desired row therein. Corresponding rows in the different storage arrays provide the corresponding eight-byte rows for the data buffer as a whole. For storage/buffer transfers, data buffer address circuitry is provided for enabling a group of eight contiguous bytes to be read out of or written into the data buffer on a single access even though some of the bytes may be located on one row of the data buffer and other of the bytes on the next row of the data buffer. For channel/buffer transfers, data buffer address circuitry is provided for enabling a group of two contiguous bytes to be read out of or written into the data buffer on a single access even though one of the bytes may be located on one row of the data buffer and the other of the bytes on the next row of the data buffer. For storage/buffer transfers, an eight-byte wrap-around data shifter is located between the data buffer and the main storage unit for enabling any necessary alignment or realignment of the data being transferred. These features enable data to be loaded into the data buffer in a packed manner and without regard to the storage word boundary alignments in the main storage unit. Among other things, this minimizes the hardware needed for buffering the data and improves the data chaining capability of the system.

Channel data buffer apparatus for a digital data processing system

A byte-addressable memory system having an array of transceivers with control logic which enables memory to be addressable on individual byte boundaries rather than on two byte (word) or four byte (longword) boundaries. The memory system has two independent even-address and odd-address segments allowing parallel access to two longwords (eight bytes or one quadword) simultaneously. Logic determines which of the eight bytes should be placed on a four byte bus and the sequential order of the bytes on the bus. The entire operation takes place in one memory cycles time period and can start at any byte address.

Bidirectional data byte aligner

Two separate address lines are provided for each storage line of local storage. One address line is connected to a first group of bytes and the second address line is connected to the remaining bytes with each storage line containing the same addressing connection. Control circuits are provided for selecting any two address lines where the combination of the two provides access to both byte groups.

Simultaneous addressing of different locations in a storage unit

A cache memory (10), between a CPU and a main memory, is employed to store vectors in a cache vector space (11). Three vector operand address registers (48-50) are employed for reading vector operand elements from said cache memory and for writing results of vector operations back into cache memory. A data path from the cache memory allows vector operand elements to be written into selected local storage registers of the CPU, and a path from the local storage registers to the cache memory includes a buffer. This apparatus allows overlapped reading and writing of vector elements to minimize the time required for vector processing.

Edward George Drimak

Papers

Simultaneous addressing of different locations in a storage unit

Vector processing hardware assist and method