A dual port video memory system includes a serial-to-parallel converter coupled to the input data port and a parallel-to-serial converter coupled to the output data port. Four-bit pixel values are clocked into the serial-to-parallel converter synchronous with an input clock signal and are provided by the parallel-to-serial converter synchronous with an output clock signal. The input and output clock signals may have different frequencies, but the negative-going edges of each of these clock signals are synchronized to the negative-going edges of a master clock signal.

Dual port video memory system having semi-synchronous data input and data output

A mechanism is described which retains a copy of a selected portion of the storage protect keys at each local storage buffer in a multiprocessing system. The mechanism reduces the amount of hardware required to retain the keys at the local buffer but allows for immediate modification of a key upon execution of a set storage key instruction.

Storage protect key array for a multiprocessing system

A system for protecting data in storage against inadvertent alteration. An access to main storage is preceded by an access to auxiliary storage. A portion of the auxiliary storage address is used to address a local storage unit for a protection key. When main storage is accessed, a portion of the main storage address is used to address the local storage unit for a storage key relating to the addressed area in main storage. The keys are compared and alteration of data at the main storage address is prevented if the keys do not match.

Storage protection system

1,154,387. Memory protection in computers. INTERNATIONAL BUSINESS MACHINES CORP. 8 Dec., 1966 [7 Jan., 1966], No. 54900/66. Heading G4A. A digital computing system inhibits access by an unprivileged instruction to conditionally protected storage locations. The multi-block main memory of a multiprogramme computer is protected by means of an associative control memory. Each word in the control memory has a programme identifier field, a block address field (specifying a mainmemory block) and four status bits. The status bits are set to 1 if the programme-block, with which the control word is associated (i.e. the portion of the associated programme in the associated block or of the associated block in the associated programme) is (a) write protected, (b) write privileged, (c) transfer protected, (d) transfer privileged, for the four status bits respectively. At each memory access by a given programme, the control word for the requesting instruction and that for the requested address are obtained from the control memory in turn by associative matching with the programme identifier and the respective block addresses. If the instruction is of the " active " type, i.e. the type which alters the contents of the requested location, an interrupt (trap) is caused if the requested location is write protected and the instruction (or rather the address it came from) is not write privileged. Interrupt is also caused if a branch (transfer of control) is attempted to a transfer protected location from a location which is not transfer privileged. In all other cases, interrupt is not caused, so, e.g. a write privileged instruction may access and alter a write protected location. Applications programmes could be write protected but have the other status bits set to 0, and control programmes could have all status bits set to 1, as a simple example. If several programmes have the same protection characteristics, a common programme identifier could be used for all of them and just one control word be provided for each relevant block.

Memory protection system

In a microprocessor system, data stored in a protected memory (12) within the same housing as the microprocessor (10) are secured by enabling access to the contents of the memory in response to an instruction only if the instruction was previously fetched from the memory (12). Protection circuitry (14) comprises a decoder (22, 24) responsive to the output of a status register in the microprocessor to operate a status signal when the microprocessor is in an instruction fetch machine cycle. The status signal is stored (26) until the protected memory (12) is selected by the microprocessor (10). Access to data in the protected memory (12) is enabled only if the status signal is stored during memory select or the microprocessor is in an I/O machine cycle for communication with a peripheral. In addition, voltage controlled switches within the housing place the bus in a HALT state during memory select unless the microprocessor is in an I/O machine cycle. The protection circuitry (14) is disabled by a fuse (36) within the housing for memory content verification. Following verification, the fuse (36) is blown to secure the memory (12).

Software protection method and apparatus

Disclosed is an electronic data storage of the type wherein data is entered and read out serially. In a conventional serial-parallel-serial configuration, data is serially entered into an input register and then transferred and stored in parallel through the main section of the storage until data is transferred in parallel to the output register from which the data is read serially. In a conventional line-addressable configuration, data is entered into and read from columns of shift registers where each column is addressable. The disclosed array combines the conventional serial-parallel-serial and the line-addressable structures into one array. By utilizing three phase clock lines and an inhibit line for each cell, the disclosed structure can be fabricated with two levels of gate electrodes.

Edwin D. Councill

Papers

Three phase line-addressable serial-parallel-serial storage array

Memory protection system

Row-column-addressable memory with serial-parallel-serial configuration