A customized checker able to calculate HBM voltage drop and to identify product circuitry prone to excessive over voltages is ideated, implemented, and successfully applied to Smart Power products. This checker is conceived as part of a complete verification flow covering all main aspects of IC designs ESD compliance.

EDA checker for identification of excessive ESD voltage drop-implementation to smart power IC's

This work describes the development of empirical simulation models for snapback-based cascode nmos ESD transistors. Behavioral language VerilogA code was used to combine regular SPICE model with TLP characteristics, at triggering voltage dependent on two gate voltages. The use of empirical models for quantitative optimization of ESD protection was demonstrated on schemes and Si.

Empirical ESD models for cascode ESD transistors

This paper proposes an investigation of a CDM (charge device model) electrostatic discharge (ESD) protection method used in submicronic input–output (I/O) structures The modeling of the commonly used ESD protection devices as well as the modeling of the breakdown caused by ESD is not accurate using traditional commercial tools, hence the need for test-chip implementation, whenever a new technology node is used in production The proposed method involves defining, implementing, testing, and concluding on one test-chip structure named generically “CDM ground resistance” The structure assesses the maximum ground resistance allowed for the considered technology for which CDM protection is assured The findings are important because they will be actively used as CDM protection for all I/O structures developed in the considered submicronic technology node The paper will conclude on the constraints in terms of maximum resistance of ground metal track allowed to be CDM protected

https://www.mdpi.com/2079-9292/10/4/443/pdf

CDM Protection Test Structure for I/O Cells in a Submicronic Technology

An Electrostatic Discharge (ESD) simulation and verification flow that has been demonstrated on a real design in bipolar technology is presented in this work. The described flow can be used to verify the level of ESD robustness of integrated circuit (IC) designs. Secondly, it is possible to identify the ESD current paths between any two nodes in the design, and the flow can determine which devices will fail in the case of a catastrophic ESD event. The presented flow is based on a graph-theory Floyd-Warshall algorithm and previously defined breaking voltage (BV) models.

Chip-Level ESD Verification Using Graph-Theory Based Approach

This article describes a systematic and scalable electrostatic discharge (ESD) verification methodology embodied in a tool called ESD IP Explorer that has been specifically implemented to cover the entire design flow and to comply with custom circuit architectures. The tool identifies the ESD protection network of a circuit thanks to a flexible topology-aware mechanism and converts the circuit description of this network into a directed graph whose edges are provided with quasistatic electrical behaviors inferred from the machine learning techniques detailed in a companion paper. A graph-based analysis establishes a risk rating cartography for all top-level pad-to-pad discharge combinations. The circuit reviewer, a chip designer, or an ESD expert can, therefore, assess the ESD performances of the ESD network under study and easily investigate potential ESD design weaknesses.

Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits—Part II

This work describes an ESD empirical simulation flow for circuits containing snapback-based devices. Regular ESD transistors SPICE models were combined with empirical models, based on TLP measurements. Behavioral language VerilogA code has been used to add measured characteristics of the transistor at triggering voltage dependent on simulated gate voltage.

Empirical ESD simulation flow for ESD protection circuits based on snapback devices

ESD transistors with multiple parallel gate terminals were measured by TLP using worst-case scenario set-up. The resulting Empirical ESD Models for multiple gates ESD transistors employ behavioral code and contain the dependency of Vt1 and post-snapback characteristics on the sizes of the multiple gates of the ESD transistor. Simulation of HBM stress, employing E2M of multi-gate ESD transistors, was demonstrated. Finally, the dependency of the coupling between the parallel gates, on the layout of the ESD transistor, was investigated.

Efraim Aharoni

Papers

Empirical ESD simulation flow for ESD protection circuits based on snapback devices

Empirical ESD models for cascode ESD transistors

Empirical ESD Modeling of Multi-Gate ESD Transistors