Open Access
Empirical ESD Modeling of Multi-Gate ESD Transistors
Efraim Aharoni,Avi Parvin +1 more
TLDR
The resulting Empirical ESD Models for multiple gates ESD transistors employ behavioral code and contain the dependency of Vt1 and post-snapback characteristics on the sizes of the multiple gates of the ESD transistor.Abstract:
ESD transistors with multiple parallel gate terminals were measured by TLP using worst-case scenario set-up. The resulting Empirical ESD Models for multiple gates ESD transistors employ behavioral code and contain the dependency of Vt1 and post-snapback characteristics on the sizes of the multiple gates of the ESD transistor. Simulation of HBM stress, employing E2M of multi-gate ESD transistors, was demonstrated. Finally, the dependency of the coupling between the parallel gates, on the layout of the ESD transistor, was investigated.read more
Citations
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Proceedings ArticleDOI
ESD-ability Enhancement of High Voltage pLDMOSs with the Discrete Source Side
TL;DR: In this article , the authors improved the ESD capability of high-voltage pLDMOSs by adding discrete HVPB distributions in the source side, which increased the conduction cross-sectional area at the source end.
References
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Book
ESD in silicon integrated circuits
TL;DR: ESD Phenomena and Test Methods The Physics of ESD Protection Circuit Elements Requirements and Synthesis of ESD Protection Circuits Design and Layout Requirements Analysis and Case Studies Modelling of ESC in Integrated Circuits Effects of Processing and Packaging.
Proceedings ArticleDOI
Dynamic gate coupling of NMOS for efficient output ESD protection
Charvaka Duvvury,Carlos H. Diaz +1 more
TL;DR: In this article, a dynamic gate coupling effect that increases the electrostatic discharge (ESD) protection efficiency of NMOS output devices is reported and the design issues for optimum output ESD protection are also discussed.
Journal ArticleDOI
Multi-finger turn-on circuits and design techniques for enhanced ESD performance and width scaling
S. Trinh,Markus Paul Josef Mergens,K. Verhaege,Cornelius Christian Russ,John Armer,Phillip Czeslaw Jozwiak,B. Keppens,Russell Mohn,G. Taylor,F. De Ranter,B. Van Camp +10 more
TL;DR: In this article, the authors present a very compact ESD protection configuration with an ESD area performance up to 5VHBM/um2 in fully silicided and silicide blocked NMOS designs.
Proceedings ArticleDOI
Empirical ESD simulation flow for ESD protection circuits based on snapback devices
TL;DR: In this article, an ESD empirical simulation flow for circuits containing snapback-based devices was described, where regular ESD transistors SPICE models were combined with empirical models, based on TLP measurements.
Proceedings ArticleDOI
Empirical ESD models for cascode ESD transistors
Efraim Aharoni,Avi Parvin,Yosi Vaserman,Alfred Yankelevich,Aharon Unikovski,Israel Rotstein,Raz Reshef +6 more
TL;DR: In this paper, the authors describe the development of empirical simulation models for snapback-based cascode nmos ESD transistors and demonstrate the use of empirical models for quantitative optimization of ESD protection.