A Three Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers (103) such that each layer may be separately optimized. One control logic circuit (101) suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory (100) involves thinning of the memory circuit (103) to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Three dimensional structure memory

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

Vertical system integration

Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.

Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers

A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.

Three dimensional device integration method and integrated device

General purpose methods for the fabrication of integrated circuits (24, 26, 28,... 30) from flexible membranes (20, 36) formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices (24, 26, 38,... 30) are formed in a semiconductor layer of the membrane (36). The semiconductor membrane layer (36) is initially formed from a substrate (18) of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multichip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Membrane dielectric isolation ic fabrication

A method for making an integrated circuit with circuit elements dielectrically isolated is described. The method involves growing an epitaxial layer on a substrate, masking where desired the epitaxial layer surface against oxidation, and sinking a thermal oxide into the epitaxial layer. A support is then mounted on the epitaxial layer top and the substrate removed, for example, by electrolytic etching. Circuit elements are built into the dielectrically isolated semiconductor regions. The technique allows the provision of connections on both sides of the regions containing circuit elements.

Method of manufacturing a semiconductor device and device manufactured by said method

A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE. BY USING A DOUBLE LAYER AS A MASKING LAYER, THE ELECTRIC PROPERIES OF TWO REGIONS WHICH ARE SITUATED IN THE SEMICONDUCTOR BODY ACCURATELY RELATIVE TO EACH OTHER CAN BE VARIED WITHOUT AN INTERIM PROCESION PHOTOMASKING STEP. THE INVENTION PROVIDES VWERY WIDE POSSIBILITIES OF APPLICATION. FOR EXAMPLE, THE FIRST REGION CAN BE DOPED WITH AN IMPURITY VIA AN APERATUS IN THE MASKING LAYER, AFTER WHICH THE LOWER COMPONENT LAYER OF THE MASKING LAYER IS UNDERETCHED AND AN IMPURITY IS THEN INTRODUCED INTO THE SECOND REGION. IT IS ALSO POSSIBLE, AFTER UNDERTCHING THE LOWER COMPONENT LAYER, TO OXIDISE THE SECOND REGION OF THE SEMICONDUCTOR BODY, AS A RESULT OF WHICH MAY IMPORTANT STRUCTURES ARE OBTAINED IN A SIMPLE MANNER.

Method of manufacturing a semiconductor device and semiconductor device manufactured by using such a method

An oxide-isolated, vertical bipolar transistor integrated circuit provided with a channel stop preventing inversion of the base region of the transistors and serving as a channel stop between buried isolation junctions, the channel stop bordering the whole of the oxide isolation.

Integrated circuit with oxidation-junction isolation and channel stop

A method of making a semiconductor device is described in which a selected surface portion of a silicon wafer is masked against oxidation, and then the surface is oxidized to grow a thermal oxide which sinks into the silicon surface at the unmasked areas, with the result that the masked silicon remains as a mesa surrounded by the sunken oxide. Then semiconductor devices can be provided by various techniques in the silicon mesa. The advantages include the provision of flat junctions, as distinguished from dish junctions in the prior art, reduced capacitance resulting from the extension of the device interconnections over the silicon wafer, and a flatter surface on top of the wafer reducing the risk of damage to the deposited interconnections.

Methods of producing a semiconductor device and a semiconductor device produced by said method

A method of making a monolithic semiconductor integrated circuit is described. On a thick silicon wafer is provided an oxidation mask in a desired pattern, and then the surface is thermally oxidized to sink into the silicon surface a sunken oxide pattern. Then impurities are introduced into the silicon surface regions to form PN junctions extending transversely to the surface. Next an insulating support is mounted on the wafer surface, and the backside is lapped or etched off until the sunken oxide pattern is reached forming silicon islands containing transverse PN junctions isolated by the silicon oxide.

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Papers

Method of manufacturing a semiconductor device and device manufactured by said method

Method of manufacturing a semiconductor device and semiconductor device manufactured by using such a method

Integrated circuit with oxidation-junction isolation and channel stop

Methods of producing a semiconductor device and a semiconductor device produced by said method

Method of manufacturing a semiconductor device and semiconductor device obtained by carrying out said method