A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

A read only memory includes a memory cell provided at an intersection between a word line and a bit line, and a plurality of reference potential transmission lines each receiving a reference potential determined in accordance with an externally applied potential designating signal. The memory cell includes a transistor element having a gate coupled to a word line, a drain coupled to a bit line and a source which is coupled to one of the reference potential transmission lines or is held in an open state. Stored data in the memory cell is changed by switching the potentials of the reference potential transmission lines. This enables storing of different data bits in one memory cell.

Read only memory for storing multi-data

A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more.

Semiconductor Integrated circuit

A master slice semiconductor integrated circuit comprising ROM memory cells which consist of NMOS-transistors as well as PMOS-transistors. In order to increase the integration density on the master slice, the NMOS-transistors and the PMOS-transistors (memory cells) in one and the same row are controlled via one and the same word line. The circuit includes row selection means, for example, an exclusive-OR circuit for each row, for selecting either a single row of NMOS cells or a single row of PMOS cells.

Master slice cmos array having complementary columns

Tracking circuitry is described for use in a memory device. The tracking circuitry can be used to monitor word line voltages in a dynamic random access memory (DRAM) and includes a comparator circuit which compares a simulated word line signal to a digit line equilibrate bias voltage. The equilibrate bias voltage is generated using either memory column circuitry or a linear resistor voltage divider.

Memory device tracking circuit

A memory circuit implemented in a CMOS array employs both P-channel and N-channel transistors as memory devices. The use of P-channel memory devices is made possible by providing a level-shifting circuit and a voltage reference circuit to compensate for manufacturing process variations and fluctuations in power supply levels. The reference circuit is made up of a series connection of P-channel FETs that are the same as the memory transistors. The reference voltage produced by the reference circuit tracks variations in the power supply and reflects changes in manufacturing processes so that they are compensated in the output of the level shifting circuit. Performance is further enhanced by clocking load FETS that connect the memory transistors to the voltage source, and density is increased by providing two word lines per row of memory transistors.

Emudadouuru Aaru Kaan

Papers

High density rom in cmos gate array