Patent
High density rom in cmos gate array
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TLDR
In this article, the use of P-channel memory devices is made possible by providing a level-shifting circuit and a voltage reference circuit to compensate for manufacturing process variations and fluctuations in power supply levels.Abstract:
A memory circuit implemented in a CMOS array employs both P-channel and N-channel transistors as memory devices. The use of P-channel memory devices is made possible by providing a level-shifting circuit and a voltage reference circuit to compensate for manufacturing process variations and fluctuations in power supply levels. The reference circuit is made up of a series connection of P-channel FETs that are the same as the memory transistors. The reference voltage produced by the reference circuit tracks variations in the power supply and reflects changes in manufacturing processes so that they are compensated in the output of the level shifting circuit. Performance is further enhanced by clocking load FETS that connect the memory transistors to the voltage source, and density is increased by providing two word lines per row of memory transistors.read more
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Patent
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References
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Patent
Semiconductor storage device
TL;DR: In this paper, the authors propose to decrease the number of bits which are stored in one ROM cell and all transistors including a decoder by converting the advance number of an input signal from an address decoder and its size of bits through a ROM cell array.
Patent
Semiconductor integrated circuit
TL;DR: In this paper, the authors proposed a scheme to attain high speed access of a RAM and a ROM without increasing the number of input terminals by selecting a data input and output terminal and a parallel input andoutput terminal according to the selection of a memory pointer register.
Patent
Master slice type semiconductor device
TL;DR: In this article, the authors proposed to always supply a stable voltage by forming a high density layer on a semiconductor pellet corresponding to the wirings of a power source in a line region, and thin forming only a field insulating film layer between the high-density layer and the power source, thereby preventing the variation in the power sources due to induction of a noise voltage of an internal circuit network.