Microring modulators (MRMs) with CMOS electronics enable compact low power transmitter solutions for 400G Ethernet and co-packaged optical transceivers. In this article, we present a 3-D-integrated 112-Gb/s pulse amplitude modulation (PAM)-4 optical transmitter (OTX) using silicon photonic MRM, on-chip laser, and co-packaged 28-nm CMOS driver. The 3- $V_{\mathrm {pp}}$ driver includes a lookup table (LUT)-based PAM-4 nonlinear equalizer to address static and dynamic MRM nonlinearities. An integrated thermal control method that is insensitive to input power fluctuations is proposed to compensate for the temperature sensitivity of MRMs. PAM-4 measurement results of our OTX at 112 Gb/s show that transmitter dispersion eye closure quaternary (TDECQ) < 1.5 dB is achieved from 28 °C to 55 °C with 7.4-pJ/bit energy efficiency including on-chip laser.

A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 Transmitter With Nonlinear Equalization and Thermal Control

This article presents a 50-Gb/s optical transmitter (TX), consisting of a 40-nm distributed CMOS driver and a 180-nm silicon-photonic modulator. A lumped-segment Mach–Zehnder modulator (LS-MZM) is developed for high bandwidth (BW) four-level pulse amplitude (PAM-4) modulation. A multi-segment driver with limiting outputs is co-designed, which is distributed into each LS-MZM segment. By grouping these LS-MSM segments in a thermometer code, high-linearity modulation is realized without the need of power-hungry high-swing linear drivers. To improve the optical PAM-4 signal integrity, in-segment multiplexing along with clock phase interpolation is adopted to synchronize the electrical and optical signals across all segments. The hybrid coupling between the driver and modulator is devised to boost the BW of the high-speed data path, while a half-rate clock and data recovery (CDR) circuit is integrated to remove the accumulated jitter. Measurements show that the TX exhibits an extinction ratio (ER) of up to 9.8 dB and a 0.99 ratio of the level mismatch. A figure-of-merit (FoM) of 1.39 pJ/bit/dB corresponds to a 682-mW power, which can be further reduced by 40%, at the cost of a degraded ER of 4 dB. The PAM-4 CDR helps to achieve $< 10^{-12}$ BER and >0.1- $\text{U}I_{\mathrm {pp}}$ jitter tolerance (JTOL) from 10 to 100 MHz.

A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR

Photonics die or integrated photonics modules co-packaged with compute engines have the potential to deliver significant improvements in power, bandwidth and reach needed to meet the computing and communication demands of data centers and other high-performance computing (HPC) systems. The challenges and solutions in co-packaging photonics modules are described through two case studies; one of a network-switch die co-packaged with socketable photonics modules and another of a Field Programmable Gate Array (FPGA) co-packaged with optical dies (tiles). The technical requirements to deliver the promise of co-packaged photonics in high volume are outlined. 

Co-Packaged Photonics For High Performance Computing: Status, Challenges And Opportunities

For the non-stop demands for a better and smarter society, the number of electronic devices keeps increasing exponentially; and the computation power, communication data rate, smart sensing capability and intelligence are always not enough. Hardware supports software, while the integrated circuit (IC) is the core of hardware. In this long review paper, we summarize and discuss recent trending IC design directions and challenges, and try to give the readers big/cool pictures on each selected small/hot topics. We divide the trends into the following six categories, namely, 1) machine learning and artificial intelligence (AI) chips, 2) communication ICs, 3) data converters, 4) power converters, 5) imagers and range sensors, 6) emerging directions. Hope you find this paper useful for your future research and works.

Trending IC design directions in 2022

We present an O-band four-level pulse amplitude modulation (PAM4) transmitter based on a dual-drive silicon modulator with binary driving electronics at CMOS voltages, effectively eliminating the need for power-hungry digital-to-analog converters (DACs) and RF drivers The fabricated dual-drive silicon modulator has cascaded p - n junction and p - i - n junction embedded in each arm of Mach-Zehnder interferometer, implementing high-speed data modulation and efficient bias control, respectively Power dissipation of around 611 fJ/bit is obtained when synthesizing 46 Gb/s PAM4, showing high power efficiency The fabricated silicon modulator exhibits a π-voltage-length product of 45 V·mm, and a 3-dB bandwidth of up to 27 GHz Meanwhile, to implement a power-efficient PAM4 transceiver, the digital signal processing (DSP) at the receiver side is also discussed by balancing the performance and complexity With a low-complexity DSP, negligible power penalty is observed after transmission over 38-km SSMF for both synthesized 20 Gb/s and 40 Gb/s PAM4 The presented PAM4 transmitter takes the advantages of both carrier-depletion and carrier-injection phase shifters for effective data modulation and bias control in PAM4 signalingand provides a power-efficient transmitter solution by eliminating the use of power-hungry DACs or RF drivers for datacenter interconnects

Power-Efficient O-Band 40 Gbit/s PAM4 Transmitter Based on Dual-Drive Cascaded Carrier-Depletion and Carrier-Injection Silicon Mach-Zehnder Modulator With Binary Driving Electronics at CMOS Voltages

The ever-increasing demand for high network capacities and escalating data centers have pushed the boundary from discrete transceivers toward the integration of monolithic electro-optical ICs [1]. Furthermore, complex modulation schemes such as PAM-4 have been introduced to improve the trade-off between circuit bandwidth, power consumption, data-rate and optical-link range compared to NRZ signaling. Therefore, the cost advantage of a fully integrated silicon solution will eventually push classical discrete implementations toward obsolescence.

Enrico Sentieri

Papers

12.2 A 4-Channel 200Gb/s PAM-4 BiCMOS Transceiver with Silicon Photonics Front-Ends for Gigabit Ethernet Applications