Showing papers by "Erdal Oruklu published in 2017"

Traffic sign recognition based on the NVIDIA Jetson TX1 embedded system using convolutional neural networks

Abstract: Traffic sign recognition is an important step for integrating smart vehicles into existing road transportation systems. In this paper, an NVIDIA Jetson TX1-based traffic sign recognition system is introduced for driver assistance applications. The system incorporates two major operations, traffic sign detection and recognition. Image color and shape based detection is used to locate potential signs in each frame. A pre-trained convolutional neural network performs classification on these potential sign candidates. The proposed system is implemented on NVIDIA Jetson TX1 board with web-camera. Based on a well-known benchmark suite, 96% detection accuracy is achieved while executing at 1.6 frames per seconds.

FPGA implementation of a support vector machine classifier for Ultrasonic flaw detection

Abstract: In this work, we investigate the hardware implementation of Support Vector Machine (SVM) prediction on an FPGA platform for industrial ultrasound applications. Specifically, SVM is used as classifier for identifying ultrasonic A-scan signals as signals with flaw or signals without flaw. Hardware acceleration using FPGA is the main theme of the presented work. The architecture used to implement the SVM prediction is discussed in detail. Synthesis results indicate that Ultrasonic flaw detection using SVM algorithm is feasible for real-time applications on programmable hardware such as FPGAs.

Comparison of GPU and FPGA based hardware platforms for ultrasonic flaw detection using support vector machines

Abstract: This study investigates the performance of different hardware platforms and development frameworks for efficient realization of an ultrasonic flaw detection algorithm based on the Support Vector Machine (SVM) classifier. The proposed algorithm is based on subband decomposition of ultrasonic signals followed by classification with a trained SVM model that uses subband filter outputs as feature inputs. Target host platforms include an FPGA-based Xilinx ZedBoard, a GPU-based Tegra System-on-Chip (SoC) and a high-performance computing (HPC) server with GPU accelerators. GPU development is done with CUDA library functions provided by NVIDIA and TensorFlow by Google. TensorFlow is a numerical computation library used primarily for building machine learning algorithms. RTL code for FPGA implementation is generated by System Generator tool by Xilinx. Implementation results show that while all platforms can achieve real-time operation with small data sets, scalability is a difficult challenge for embedded hardware. TensorFlow provides the shortest development time and enables code migration from servers to embedded systems.

Security challenges and solutions for closed-loop artificial pancreas systems

Abstract: This work presents security solutions related to multi-sensor closed-loop artificial pancreas (AP) systems The proposed AP system is built on a heterogeneous platform incorporating a smartphone, activity sensors, a glucose monitor, an insulin pump, a laptop hosting the multi-variable control algorithm and a cloud server Developing a secure AP system is essential for mass adoption among diabetes patients However, various communication interfaces and dynamics among the AP components result in multiple security vulnerabilities and intrusion points We first identify the threats related to both AP data communication and AP data storage Then, we propose several cryptography and authentication measures to address the threats related to the man-in-the-middle attacks

Performance analysis of deep learning architectures for ultrasonic NDE applications

Abstract: Research on Deep Learning algorithms has progressed rapidly in recent years. Since the inception of deep learning, numerous architectures have been proposed for various applications targeting pattern recognition, image, audio and information analysis. For example, often audio signal classifications use variations of Deep Belief Networks (DBN), while a Deep Neural Network (DNN) called AlexNet is widely used for handwriting and alphabet recognition. Convolutional Neural Network (CNN) and its derivatives are primarily used in machine vision and imaging applications. Convolutional Deep Belief Networks (CDBN) work as a combination of CNN and DBN architectures and can be applied to image, audio and multimodal data. There has been limited studies on the effectiveness of these architectures for ultrasonic NDE applications. Therefore, this work investigates new flaw detection methods based on recent advances on deep learning architectures.

A hardware/software co-design architecture for ultrasonic flaw detection with Hidden Markov Model and Wavelet Transform

Abstract: This work presents an embedded hardware architecture for real-time ultrasonic NDE applications that incorporate Hidden Markov Model (HMM) based statistical signal methods. Proposed algorithm is a combination of Discrete Wavelet Transform (DWT) for pre-processing A-scan signals and HMM for classification of the flaw presence. For this study, a MicroZed FPGA with Xilinx Zynq-7020 System-on-Chip (SoC) is chosen for the hardware implementation. A hardware/software approach is used for maximizing the resource usage and efficiency. Wavelet transform has been implemented on the ARM CPU core while the HMM has been implemented on FPGA fabric. Results confirm that the algorithm is feasible for real-time implementation on this low-cost SoC, with an execution time under 40ms.

Hardware and Software Implementation of an Artificial Pancreas System on a Mobile Device

Abstract: In this work, an artificial pancreas AP system, implemented on a mobile device is described. The proposed AP platform integrates hardware insulin pump, glucose monitor, various sensors for vital signs and physical activities and software closed-loop control algorithm, sensor fusion, data storage and remote server access components via smartphone that is running a dedicated Operating System designed for AP systems. Interfacing with this OS and custom application development steps are presented. Closed loop operation is demonstrated with case studies.