This paper explores a low standby power 10T (LP10T) SRAM cell with high read stability and write-ability (RSNM/WSNM/WM). The proposed LP10T SRAM cell uses a strong cross-coupled structure consisting standard inverter with a stacked transistor and Schmitt-trigger inverter with a double-length pull-up transistor. This along with the read path separated from true internal storage nodes eliminates the read-disturbance. Furthermore, it performs its write operation in pseudo differential form through write bitline and control signal with a write-assist technique. To estimate the proposed LP10T SRAM cell’s performance, it is compared with some state-of-the-art SRAM cells using HSPICE in 16-nm CMOS predictive technology model at 0.7 V supply voltage under harsh manufacturing process, voltage, and temperature variations. The proposed SRAM cell offers 4.65X/1.57X/1.46X improvement in RSNM/WSNM/WM and 4.40X/1.69X narrower spread in RSNM/WM compared to the conventional 6T SRAM cell. Furthermore, it shows 1.26X/1.08X/1.01X higher RSNM/WSNM/WM and 1.71X/1.25X tighter/wider spread in RSNM/WM compared to the best studied SRAM cells. The proposed SRAM cell indicates 74.48%/1.41% higher/lower read/write delay compared to the 6T SRAM cell. Moreover, it exhibits the third-(second-) best read (write) dynamic power, consuming 29.69% (26.87%) lower than the 6T SRAM cell. The leakage power is minimized by the proposed design, which is 37.35% and 12.08% lower than that of the 6T and best studied cells, respectively. Nonetheless, the proposed LP10T SRAM cell occupies 1.313X higher area compared to the 6T SRAM cell.

A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins

Single-ended half-select disturb-free 11T static random access memory cell for reliable and low power applications

The internet of things (IoTs)-based systems require battery-enabled energy-efficient memory circuits to operate at low voltage domain, especially below the transistor’s threshold. This study presents a single-ended 7T SRAM cell for IoTs applications. Cell core of the proposed 7T SRAM cell is composed of a novel Schmitt-trigger circuit in which a dynamic body bias technique is applied to a standard CMOS inverter through a feedback mechanism, whereby the threshold voltages of two MOSFETs can be changed, thus changing the switching voltage. The proposed 7T SRAM cell employs only one bitline to perform both read and write operations to reduce active power consumption. Read operation of the proposed 7T SRAM cell is conducted using only a single n-type MOSFET transistor driven by QB node. This transistor isolates bitline from storage nodes during read operation, improving read stability (RSNM) and read delay (TRA). A p-type MOSFET controlled by write wordline is placed inside the cell core to cut its feedback path off during write operation. This mechanism eliminate writing ‘1′ issue in single-ended SRAM cell and facilitate write ‘1′ operation, resulting in write-ability (WSNM) enhancement. To prove superiority of the proposed 7T SRAM cell in the various design metrics, it is compared with six state-of-the-art SRAM cells at subthreshold supply of VDD = 0.3 V. The proposed 7T SRAM cell is the second/first/third best cell in terms of RSNM/WSNM/write access time (TWA). Furthermore, an improvement of at least 2.55X in TRA and 12.58X (2.02X) in read (write) energy consumption is achieved by the proposed 7T SRAM cell. Although, the proposed 7T SRAM cell offers some disadvantages, nevertheless it offers the best proposed figure of merit.

Design of a Schmitt-Trigger-Based 7T SRAM cell for variation resilient Low-Energy consumption and reliable internet of things applications

Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design

Ultra-low-power and stable 10-nm FinFET 10T sub-threshold SRAM

Graphene nanoribbons (GNRs) are a good replacement material for silicon to overcome short-channel effects in nanoscale devices. However, with continuous technology scaling, the variability of device parameters also increases. Indeed, process, voltage, and temperature (PVT) variations affect the performance of GNR devices because of their small size. Moreover, the bandgap of GNRs is strongly affected by the number of carbon atoms across the channel width. This paper accurately evaluates the impact of such PVT variations on the performance of circuits based on Schottky barrier (SB)-type GNR field-effect transistors (SB-GNRFETs) in terms of their timing parameters, power, and energy–delay product (EDP). Extensive simulations and stability analysis are performed on both flip-flop and conventional six-transistor static random-access memory (6T SRAM) cells made using SB-GNRFETs under these variations. A statistical analysis of the impact of the PVT variations on the SB-GNRFET-based flip-flop is also performed using Monte Carlo simulations, considering the variation of one or all of the parameters, with or without line-edge roughness effects.

Erfan Abbasian

Papers

A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins

Single-ended half-select disturb-free 11T static random access memory cell for reliable and low power applications

A variation-aware design for storage cells using Schottky-barrier-type GNRFETs

Design of a Schmitt-Trigger-Based 7T SRAM cell for variation resilient Low-Energy consumption and reliable internet of things applications

Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design