Showing papers by "Eric Beyne published in 1994"

Accelerated Ageing with In Situ Electrical Testing: A Powerful Tool for the Building-In Approach to Quality and Reliability in Electronics

Abstract: A new technique for reliability and quality optimization of electronic components and assemblies, the so called in situ accelerated ageing technique with electrical testing, is presented. This technique is extremely useful for the building-in approach to quality and reliability. First, it can be used to optimize an electronic component or assembly with respect to its quality and reliability performance at a very early stage, i.e. at the design level, at the level of materials selection, and at the level of identifying production techniques and defining production parameters. The typical test time is of the order of 24 hours, which is sufficiently short to allow a design of experiments type approach to quality and reliability optimization. Furthermore, the technique is also very useful for obtaining a deeper understanding of the physico-chemical processes which lead to failure. A number of practical examples where the technique has been successfully applied are discussed.

Design of an optimal heat-sink geometry for forced convection air cooling of Multi-Chip Modules

Abstract: An assessment is made of the limits to the cooling capability of forced convection air cooling of multi-chip modules. Therefore heat-sinks of different geometries are analysed, using a new design criterion which involves both the effects of heat transfer performance and pressure drop. It is shown that, when pressure drop is taken into account, plate fin heat-sinks have a better cooling performance than offset-strip fin or pin fin heat-sinks. The dimensions of a plate-fin heat-sink are optimized using an analytical model. The optimal plate-fin heat-sink has a cooling performance comparable to what is normally achieved by integral water cooling. To confirm the thermal performance of the optimal plate fin heat-sink, measurements are carried out in a low speed windtunnel.

Modelling of thermal vias in thin film multichip modules

Abstract: A semi-analytical model is presented for evaluating the thermal resistance of via networks used in thin film multichip modules. Correlations between dimensionless groups were derived from numerical data. Therefore, the via network was divided in three basic elements. This allows one to reconstruct the network as a series and parallel connection. The results of this semi-analytical model are compared with those of an existing analytical model and a 3D finite element model. Good agreement between the three models was obtained. The heat conduction efficiency of a staggered thermal via network is defined and the influence of several parameters was investigated. >

CIMID, a technology for high density integration of electronic systems

Abstract: CIMID stands for chip In Moulded interconnect &vice [I]. This new technology is a combination of moulded 3D-interconnections (SIL@)[2], chip-on-board (COB) and MCM-D E31 technology. A schematic view of a module cross-section is shown in figure 1. Substrate features such as cavities for attaching bare die and via holes are directly realised by the moulding process. As moulding tecfitlology is used, additional € t z ” s such as connectors and special substrate shapes may be integrated. The thermoplastic substrates are metallised using printed circuit board techniques. Patterning of the non-planar surfaces is performed by laser imaging. A thin film dielectric is applied and patterned on this substrate. Photosensitive BCB is used for this application because of its low curing temperature. On top of this dielectric layer, a thin film metallisation is applied. Because of the small via size in the dielectric layer and the small conductor width in the thin film metailisation, a high wiring densiry is obtained. Furthermore, as cavities are used for mounting the devices, a very thin circuit can be realised. Because of all these features, CIMID technology offers the possibility to integrate a complex electronic system on a single substrate with small dimensions.