E
Eric Sprangle
Researcher at Intel
Publications - 24
Citations - 1820
Eric Sprangle is an academic researcher from Intel. The author has contributed to research in topics: Cache pollution & Cache. The author has an hindex of 12, co-authored 24 publications receiving 1805 citations.
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Patent
Method and apparatus for determining a dynamic random access memory page management implementation
Eric Sprangle,Anwar Rohillah +1 more
TL;DR: In this article, the authors present a system and method for a processor to determine a memory page management implementation used by a memory controller without necessarily having direct access to the circuits or registers of the memory controller.
Patent
Method and apparatus for prefetching data to a lower level cache memory
TL;DR: In this paper, a prefetching scheme is proposed to detect when a load misses the lower level cache and hits the next level cache, which may result in initiating a sidedoor prefetch load for fetching the previous or next cache line into the lower-level cache.
Patent
Speculative scheduling of instructions with source operand validity bit and rescheduling upon carried over destination operand invalid bit detection
TL;DR: A data validity circuit coupled to the one or more source registers to determine the validity of the data in the source registers, and to indicate the validity in a destination register based upon the validity bit in the at least one source register as discussed by the authors.
Patent
Mechanism to increase data compression in a cache
TL;DR: In this article, the authors present a computer system consisting of a central processing unit (CPU) and a cache memory coupled to the CPU, which includes a main cache having plurality of compressible cache lines to store additional data, and a plurality of storage pools to hold a segment of the additional data for one or more of the plurality of cache lines that are to be compressed.
Patent
Providing Extended Cache Replacement State Information
Andrew T. Forsyth,Ramacharan Sundararaman,Eric Sprangle,John Mejia,Douglas M. Carmean,Edward T. Grochowski,Robert Dale Cavin +6 more
TL;DR: In this paper, a processor includes a decode logic to receive and decode a first memory access instruction to store data in a cache memory with a replacement state indicator of a first level, and to send the decoded first-level access instructions to a control logic.